主板上電過程

1、主板上電過程主板上電過程Willess2009/6/10前言n電腦的開機(jī)只需要對(duì)著Power鍵輕輕一按即可.n可這一按具體是如何使電腦能開機(jī)工作的呢?它的整個(gè)過程是怎樣的?n以下分幾個(gè)部分做講解Contentn開機(jī)上電動(dòng)作圖解n主板的電壓定義n主板的主要開機(jī)信號(hào)介紹n主板開機(jī)上電過程（波形和電路）PWRBTNSlp-s3(+)Pson#(-)+5v/-5v+3v+12v/-12v+5v+3vPower okPower okNB_ RESETResetSBNBCPUPOWERSUPER I/OOR AS016Cpu rstIntel chipset power on sequencePwr ok

2、Power SequenceMB Power Sequence主板基本電壓POWERSpecification +12V11.4 12.6V -12V-10.8 13.2V +5V4.75 5.25V +3.3V3.14 3.47V +5VSB4.75 5.25V n主板基本電壓有5個(gè)，其他電壓都是由這5個(gè)基本電壓轉(zhuǎn)換而得. 主板基本電壓Item Global StatesSleepingStatesDetail description1G0S0電腦的正常工作狀態(tài)電腦的正常工作狀態(tài)-作業(yè)系統(tǒng)和應(yīng)用程式都在執(zhí)行作業(yè)系統(tǒng)和應(yīng)用程式都在執(zhí)行2G1S1最耗電的睡眠模式最耗電的睡眠模式,所有原件均有保持

3、電源，除了一些沒有被所有原件均有保持電源，除了一些沒有被使用的使用的device.S3Suspend to RAM，只有，只有memory是唯一有電源供給的原是唯一有電源供給的原件件 ,XP系統(tǒng)下叫做系統(tǒng)下叫做“待機(jī)待機(jī)(Standby)”, Vista叫做叫做“睡眠睡眠(Sleep)”.S4Suspend to HDD，在，在Windows中叫休眠中叫休眠(Hibernation ）,所所有主記憶體儲(chǔ)器的內(nèi)容被儲(chǔ)存在硬碟中，從有主記憶體儲(chǔ)器的內(nèi)容被儲(chǔ)存在硬碟中，從S4恢復(fù)後，使用恢復(fù)後，使用者可以恢復(fù)到原本的工作狀態(tài)者可以恢復(fù)到原本的工作狀態(tài).3G2S5Soft off，只有，只有stand

4、by power 存在存在.4G3BatteryMechanical Off，Power cord被拔掉，只有被拔掉，只有Battery.ACPI的Global States分四個(gè)狀態(tài)G0G1G2G3主板基本電壓狀態(tài)電壓種類有狀態(tài)電壓種類有3種種n1.Main power: S0/S1n2.Dual power:S0/S1/S3n3.Standby power:S0/S1/S3/S4/S5詳細(xì)參考附件：詳細(xì)參考附件：Main Power Main power的產(chǎn)生由的產(chǎn)生由SLP_S3#去控制去控制。 按Power Button PWRBTN#拉low 通知SIOSIO告知NB NB送出SLP

5、_S3#(此時(shí)SLP_S3#為高電平) PSON# 被拉low Power Supply產(chǎn)生Main Power. Power-up (Main Power)CH1:+12VCh2:+5VCh3:+3V1.Main power (+12V,+5V,+3V) almost ramp up at the same time.2.The main power ramp behavior depends on the power supply design.Standby Power 1， 在MB上，power supply只提供+5VSB一種standby電壓, 其他standby power都由它

6、轉(zhuǎn)出來的。 2，Standby power上電(插上power cord)主板就會(huì)有，但其提供的電流有限。 Dual Power Dual power由standby power和main power提供，他存在於S0,S1,S3這幾種狀態(tài)下，由Gate信號(hào)去控制哪一個(gè)power輸出。 主板信號(hào)簡(jiǎn)介nRSMRST#nSLP_S3#nPS_ON#nPWROKnPLTRST#Battery3.0VBATT2.6VG3 State1.BATT comes from BATTERY at G3 state. So BATT will be 2.6V at G3 state.2.BATT comes f

7、rom +3VSB at S5 state. So BATT will be 2.9V at S5 state. S5 State2.9VnRTCRST#有效:在G3狀態(tài)時(shí),拔掉battery,此時(shí)SB收到低電平,會(huì)清掉COMS 內(nèi)容;若要給主板維持時(shí)間或CMOS內(nèi)容, RTCRST信號(hào)需要是高電平. +3VSBS5 State+5VSBRSMRST1.After plugging power cord, +5VSB ramps up.2.+3VSB is regulated from +5VSB.3.32ms after +3VSB ramps above VTRIP (2.2V), RSM

8、RST asserts.4.RSMRST will re-assert after AC power loss, which acts like a wake up event of SB and causes the de-assertion of SLP_S3# to turn on the system.RSMRST#Resume reset active表示所有的standby power都OK.RSMRST#: Resume Well Reset, this signal is used for resetting the resume power plane logic.AUXOK

9、 Logic Example:1. Let VPQ3.1 ramps up slower than +3VSB. It is to meet the spec that RSMRST(AUXOK) needs to ramp up after VTR is ready with a delay (20ms for SB600).2. To precisely estimate the resulting delay from +3VSB to AUXOK, we need to implement the RC charge formula.VCIf VCC=3.3V, assuming 20

10、ms is needed:1. t=RC=20ms VC(20ms)=2.08V VC(18.63ms)=2VIf VCC=5V, assuming 20ms is needed:2. t=RC=20ms VC(20ms)=3.16V VC(10.22ms)=2V RC is chosen by substituting VC(t), VCC, t and solve for RC.RSMRST#PWRBTN#PWRBTN#1. Pin6 and pin8 is connected to the power button on the chassis. 2. Pressing power bu

11、tton generate a low pulse to SB and SIO.3. Power button can be programmed to generate suspend, hibernate or shut-down event.4. Generally PWRBTN# of SB is internal pulled high, R1336 is reserved to avoid internal pull-high malfunction. This must be pulled to standby power.5. CB918 must be installed:

12、1. Debounce, 2. Prevent ESD from directly going into SB and SIO. 1000PF is a commonly used value.6. To achieve better ESD resist performance, CB918 should be placed near front panel header.SLP_S3#nSLP_S3#: Sleep Control,SLP_S3# is for power plane control. This signal shuts off power to all non-criti

13、cal systems when in S3(Suspend to RAM),S4(Suspend to Disk), or S5 states.SLP_S3#PWRBTN#SLP_S5#SLP_S3#PS_ON#S0 StatePress Power Button1.In Intel platform, SLP_S3# is always used to turn on the power supply.2.When resuming from S3/S4, any wake up event will cause the de-assertion of SLP_S3#SLP_S5#, an

14、d the rest of the power-up power sequence is the same with those resuming from S5.3.Some SIO, ex:SMSC5127, uses inverted SLP_S3# to generate nPS_ON#.4.In SIS platform, PS_ON# is generated from SB itself (ex:SIS 968).+12V,+5V,+3VATX POWERS0S1S3S4S5SLP_S3#HHLLLSLP_S4#HHHLLSLP_S5#HHHHLSLP_S4#PSON# PSON

15、# 是低有效信號(hào),當(dāng)此信號(hào)為L(zhǎng)ow時(shí),Power Supply送出+3.3V,+5V,-5V,+12V,-12V等電壓. 而當(dāng)此信號(hào)被拉High時(shí),Power Supply停止送出上面的電壓. 利用此信號(hào)可以設(shè)計(jì)“ Soft Power down” 的關(guān)機(jī)功能. 當(dāng)使用者對(duì)作業(yè)系統(tǒng)下關(guān)機(jī)命令時(shí). 作業(yè)系統(tǒng)亦可關(guān)閉所有的應(yīng)用程式並利用此腳的功能達(dá)到自動(dòng)關(guān)機(jī)的動(dòng)作.灰色: +5V Power OK signal綠色: +5V (PS_ON#,電源工作電壓)PSON#在主板上,未開機(jī)時(shí)(S5時(shí)), 此信號(hào)PSON#一直被pull up到+5VSB.?當(dāng)User按下Power Button後,一般由S

16、uper I/O將此信號(hào)拉low,從而通知Power Supply送電.當(dāng)實(shí)驗(yàn)時(shí),可以直接把Power supply的PSON#用導(dǎo)線與GND瞬間導(dǎo)通,則此時(shí)Power Supply開始工作.PWROKnPWROK有的資料也叫PWRGD, 是電源準(zhǔn)備OK的信號(hào).Power Supply 中會(huì)有PWROK,更多的在主板上,且分很多種, 如CPU_PWRGD, NB_PWRGD, VRMPWRGD, VTT_PWRGD.n當(dāng)電源送出的+3.3V and +5V達(dá)到Normal值的95%時(shí),由Power Supply送出此信號(hào).當(dāng)+3.3V or +5V 掉到Normal的95%以下時(shí),Power

17、Supply就會(huì)把此信號(hào)拉Low.當(dāng)主板收到此信號(hào)時(shí),表明電源已經(jīng)準(zhǔn)備ok,可以開始動(dòng)作. n但是大部分情況下,我們不會(huì)使用此信號(hào)來通知主板動(dòng)作 (主板上此PIN一般空接) .而是使用專門的ASIC來偵測(cè)+3.3V and +5V電壓,當(dāng)電源發(fā)出的電壓符合要求時(shí),由ASIC發(fā)出PWROK信號(hào)通知主板動(dòng)作.PS. ASIC:Application Specific Integrated Circuit,是專用集成電路.目前,在集成電路界ASIC被認(rèn)為是一種為專門目的而設(shè)計(jì)的集成電路 PWROKnThe PWRGD_3V is a function of PWRGD_PS, nSLP_S3 and

18、 nFPRST.nThe 1-0 transition of nSLP_S3 will cause an immediate 1-0 transition of PWRGD_3V.nThe 0-1 transition of PWRGD_PS will cause a 0-1 transition of PWRGD_3V. The PWRGD_3V is either immediate of after a 100ms to 120ms delay from the 0-1 transition of PWRGD_PS.+12V+5V3.3VS0 StatePS_ON#PWRGOOD_PS4

19、00msPWRGD_3V12V5V3.3VPLTRST#nPLTTST信號(hào)是對(duì)所有信號(hào)是對(duì)所有main Power信號(hào)的信號(hào)的reset進(jìn)行時(shí)序控制進(jìn)行時(shí)序控制.上電原理nPower-up SequencenG3 StatenG3-S5nS5-S0nS3-S0nPower-Down SequencenS0-S5nS0-G3 (AC Power Loss)上電原理n開機(jī)上電過程ATXPOWERMOSICHMCHSIOCPUSW_ON#5VSBPS_ON#PWRGD_PSH_PWRGD SLP_S3#32.768KHZ PWRGD_3VPWRGD_3VPWRGD_3VPWRGD_3V +/-12V

20、+/-5V3.3V3VSB3VSB上電原理:上電過程上電過程n上電源由5VSB3VSB,按開關(guān)後,SW_ON#對(duì)地short被拉低,發(fā)到ICH,使SLP_S3#拉高,SIO偵測(cè)到此信號(hào)後,拉低PS_ON#,同時(shí)把PS_ON#送到電源,此時(shí)電源發(fā)出+/-12v,+/-5v,+3.3v電壓,待穩(wěn)定輸出90%後,電源發(fā)出PWRGD_PS至SIO,SIO再發(fā)出PWRGD_3V至南北橋,南橋偵測(cè)到此信號(hào)後發(fā)出H_PWRGD至CPU.此時(shí)主板開始工作. 電源時(shí)序電源時(shí)序 1. PC電源不僅輸出電壓，還要與主機(jī)板有信號(hào)聯(lián)繫，兩者在時(shí)間次序上有一定的關(guān)係，這就叫做時(shí)序。時(shí)序是電源與主機(jī)板良好配合的重要條件，也是導(dǎo)致電腦無(wú)法正常開關(guān)機(jī)，以及電源與主機(jī)板不相容的最常見原因。 2.時(shí)序中最重要的是電源輸出電壓(通常以+5V為代表)與P.G信號(hào)，以及PS_ON#信號(hào)之間的關(guān)係。P.G信號(hào)由電源控制，代表電源是否準(zhǔn)備好，PS_ON#信號(hào)則由主機(jī)板控制，表示是否要開機(jī)。 3.兩個(gè)信號(hào)都是通過24芯的主機(jī)板電源線來連接的，電腦開關(guān)機(jī)的工作過程是這樣的：電源在交流線通電後，輸出一個(gè)電壓+5VSB到主機(jī)板，主機(jī)板上的少部分線路開始工