ALU與ALU控制器設(shè)計(jì)

1、實(shí)驗(yàn)三 ALU與ALU控制器設(shè)計(jì)姓名：葛鑫 學(xué)號：091220033 郵箱：xingenju一、實(shí)驗(yàn)?zāi)康?、了解并掌握ALU的工作原理和ALU所要完成的算術(shù)運(yùn)算與邏輯運(yùn)算。2、掌握ALU控制器的工作原理和作用。二、實(shí)驗(yàn)設(shè)備1、裝有Quartus II的計(jì)算機(jī)一臺(tái)。2、Altera DE2-70開發(fā)板一塊。三、實(shí)驗(yàn)任務(wù)1、用Verilog HDL語言戒VHDL 語言來編寫，實(shí)現(xiàn)MIPS32位的ALU及ALU的控制器，使其能夠支持基本的指令。2、用Verilog HDL語言戒VHDL 語言來編寫，實(shí)現(xiàn)RAM32位的ALU及ALU的控制器，使其能夠支持基本的指令。四、實(shí)驗(yàn)原理與電路圖1、MIPS中A

2、LU控制器的原理 在MIPS中，ALU可執(zhí)行的功能與操作如下表，需要三位控制信號： 除運(yùn)算結(jié)果result_final，ALU還輸出信號zero, less，overflow， carry分別表示運(yùn)算結(jié)果是否為0，兩數(shù)比較是大還是小，是否有溢出，以及是否有進(jìn)位，以用于某些判斷指令。為提高ALU的控制效率，ALU采用兩級控制，即通過ALU控制器實(shí)現(xiàn)對ALU的控制，而不是直接控制ALU。ALU控制邏輯圖：AluOp : 4位1. 最低位為控制加減法以及前導(dǎo)0還是前導(dǎo)1，有誤無需額外譯碼2. 倒數(shù)第二位控制作有無符號判定，有無符號數(shù)判定大小邏輯不同（less標(biāo)志）3. 兩個(gè)有符號數(shù)比較，V異或S的結(jié)

3、果為less4. 兩個(gè)無符號數(shù)比較，C的結(jié)果為less2、ARM中ALU控制器的原理AluOpAluCtr指令功能0 0 0 01 0 1ADD加法運(yùn)算0 0 0 11 0 1ADC帶進(jìn)位的加法運(yùn)算0 0 1 01 0 1SUB減法運(yùn)算0 0 1 11 0 1SBC帶進(jìn)位的減法運(yùn)算0 1 0 00 0 0BIC位清除指令0 1 0 10 0 1AND與操作0 1 1 00 1 0ORR或操作0 1 1 10 1 1EOR異或操作1 0 0 01 0 0CMN負(fù)數(shù)比較1 0 0 11 0 0TST位測試指令1 0 1 01 0 0CMP比較指令1 0 1 11 0 0TEQ相等測試指令A(yù)DD：若

4、ADD r0, r1, r2 ，則r0 = r1+r2；ADC：若ADC r0, r1, r2 ，則r0 = r1+r2+C；SUB：若SUB r0, r1, r2 ，則r0 = r1-r2；SBC：若SBC r0, r1, r2 ，則r0 = r1+r2+C-1；BIC：A中值與B中值的反碼進(jìn)行與操作；AND：按位與操作；ORR：按位或操作；EOR：按位異或操作；CMN：A加B，若小于零則結(jié)果為1，不保存減的結(jié)果；TST：A和B進(jìn)行按位與操作，全零則結(jié)果為1；CMP：A減B，若小于零則結(jié)果為1，不保存減的結(jié)果；TEQ：A和B進(jìn)行按位異或操作，全零則結(jié)果為1。五、實(shí)驗(yàn)步驟（一）Ex1（MIPS

5、的ALU及ALU控制器）1、變量名列表輸出變量名變量名類型變量名含義說明定義該變量的程序模塊名Operand_A32位input第一個(gè)操作數(shù)mips_aluOperand_B32位input第二個(gè)操作數(shù)mips_aluAluOp4位input控制變量mips_aluResult_final32位output輸出結(jié)果mips_aluCarry1位output進(jìn)位mips_aluZero1位output判零mips_aluOverflow1位output判斷溢出mips_aluLess1位output比較兩數(shù)大小mips_aluresult32位reg數(shù)組用于存放結(jié)果的臨時(shí)變量mips_alui1

6、位integer用于計(jì)數(shù)的臨時(shí)變量mips_alucount32位reg用于存放擴(kuò)展位的臨時(shí)變量mips_aluextendA，extendB32位reg用于存放擴(kuò)展后數(shù)據(jù)的臨時(shí)變量mips_alutempA，tempB32位reg用于存放數(shù)據(jù)的臨時(shí)變量mips_alutemp33位reg用于存放數(shù)據(jù)經(jīng)過加法器運(yùn)算后的臨時(shí)變量mips_aluCarry_f1位reg用于存放數(shù)據(jù)經(jīng)過加法器運(yùn)算后的進(jìn)位mips_aluSign1位reg用于存放數(shù)據(jù)經(jīng)過加法器運(yùn)算后的符號位mips_alu2、代碼module mips_alu(input31:0 Operand_A, input31:0 Opera

7、nd_B, input3:0 AluOp, output reg31:0 Result_final, output reg Carry, output reg Zero, output reg Overflow, output reg Less ); reg31:0 result6:0; always begin result1 = Operand_A Operand_B; result2 = Operand_A | Operand_B; result3 = (Operand_A | Operand_B); result4 = Operand_A & Operand_B; end in

8、teger i; reg31:0 count;reg31:0 extendA, tempA;alwaysbegin if (AluOp0 = 0) begin extendA = 0; end else beginextendA = 321'b1; end tempA = (Operand_A extendA); count = 32; for (i = 31; i >= 0; i = i-1) begin if (tempA31-i = 1) begin count = i; end end result0 = count; end reg31:0 extendB, tempB

9、; reg32:0 temp;reg Carry_f; reg Sign;alwaysbegin if(AluOp0 = 0) begin extendB = 0; end else begin extendB = 321'b1; end tempB = (Operand_B extendB); temp = Operand_A + tempB + AluOp0; result6 = temp31:0; Carry_f = temp32; Carry = Carry_f AluOp0; if (AluOp0 = 1 && temp = 0) Zero=1; else Z

10、ero=0; if (Operand_A31 = tempB31 && temp31 != Operand_A31) Overflow = 1; else Overflow = 0; Sign= temp31; if (AluOp1 = 1) Less = Carry; else Less = Sign Overflow; if (Less = 1) result5 = 321'b1; else result5 = 0; end reg2:0 AluCtr; always begin AluCtr2 = (AluOp3) & (AluOp1) | (AluOp3

11、) & AluOp2 & AluOp0); AluCtr1 = (AluOp3) & (AluOp2) & (AluOp1) | (AluOp3) & AluOp2 & AluOp1 & AluOp0) | (AluOp2) & (AluOp1) & (AluOp0); AluCtr0 = (AluOp3 & (AluOp2) & (AluOp1) | (AluOp3) & AluOp2 & AluOp0); end always begin case (AluCtr) 3'b000

12、: Result_final = result0; 3'b001: Result_final = result1; 3'b010: Result_final = result2; 3'b011: Result_final = result3; 3'b100: Result_final = result4; 3'b101: Result_final = result5; 3'b110: Result_final = result6; endcaseendendmodule3、仿真結(jié)果：功能仿真：仿真結(jié)果說明：AluOp功能Operand_AOper

13、and_BResult_finalCarryZeroOverflowLess0000加法01100000000000000000000000000000011000000000000000000000000000001100000000000000000000000000000000100001有符號減法00000000000000000000000000000010000000000000000000000000000001011111111111111111111111111111110110010010前導(dǎo)零0000000000000000000000000000000000000000

14、00000000000000000010000000000011前導(dǎo)一111000000000000000000000000000000000000000000000000000000000001100000100與00000000000000000000000000001010000000000000000000000000000011000000000000000000000000000000100000000101slt/slti00000000000000000000000000000001000000000000000000000000000000111111111111111111

15、111111111111111110010110或00000000000000000000000000001010000000000000000000000000000011000000000000000000000000000000111000000111sltu/sltiu00000000000000000000000000000001000000000000000000000000000000111111111111111111111111111111111110011000或非0000000000000000000000000000101000000000000000000000000

16、0000011001111111111111111111111111111000100001001異或0000000000000000000000000000101000000000000000000000000000001100000000000000000000000000000001101001（二）Ex2（ARM的ALU及ALU控制器）1、變量名列表輸出變量名變量名類型變量名含義說明定義該變量的程序模塊名Operand_A32位input第一個(gè)操作數(shù)arm_aluOperand_B32位input第二個(gè)操作數(shù)arm_aluAluOp4位input控制變量arm_aluC_before_

17、move1位input標(biāo)志位arm_aluctr_LRAL2位input控制位arm_aluctr_RRX1位input控制位arm_aluS5位input控制位arm_aluResult32位output輸出結(jié)果arm_aluCarry1位output進(jìn)位arm_aluZero1位output判零arm_aluOverflow1位output判斷溢出arm_aluLess1位output比較兩數(shù)大小arm_alu2、代碼module arm_alu (Operand_A,Operand_B,AluOp,Carry,Less,Zero,Overflow,Result,ctr_LRAL, ctr

18、_RRX, S, C_before_move);input 31:0Operand_A;input 31:0Operand_B;input 3:0AluOp;input4:0 S;input1:0 ctr_LRAL; input ctr_RRX; input C_before_move; output Carry,Less,Zero,Overflow;output 31:0Result; wire C_after_move; wire 31:0Result_f;wire Carry_f,Sign;wire 2:0Control;wire 31:0x0,x1,x2,x3,x4,x5;wire 3

19、1:0A,B;wire 31:0larger, out_move;wire Cin,inCarry0,inCarry1,inx4_01, inx4_11;control f_4to3(AluOp,Control);larger1to32 f_larger(AluOp1,larger);ARM_move f_move(Operand_B, S, ctr_LRAL, ctr_RRX, out_move, C_before_move, C_after_move);assign A = Operand_A;assign B = out_move larger;mux_2to1 f_toCin(AluO

20、p1, C_after_move, AluOp0, Cin);alladd f_add(A,B,Cin,Result_f,Carry_f,Zero,Overflow,Sign);assign inCarry0 = Carry_f AluOp1;assign inCarry1 = C_after_move;mux_2to1 f_toCarry(inCarry0, inCarry1, ctr_RRX, Carry);assign Less = Overflow Sign;assign x0 = (out_move) & Operand_A;assign x1 = Operand_A &am

21、p; out_move;assign x2 = Operand_A | out_move;assign x3 = Operand_A out_move;test_all0 g1(x1, inx4_01);test_all0 g2(x1, inx4_11);mux_4to1 f_getx4(Less,inx4_01,Less,inx4_11,AluOp1:0,x4);assign x5 = Result_f;mux32_6to1 f_getResult(x0,x1,x2,x3,x4,x5,Control,Result);endmodulemodule control(ALUop,ALUctr);

22、input 3:0ALUop;output reg2:0ALUctr;always(ALUop)case(ALUop)4'b0000: ALUctr = 3'b101;4'b0001: ALUctr = 3'b101;4'b0010: ALUctr = 3'b101;4'b0011: ALUctr = 3'b101;4'b0100: ALUctr = 3'b000;4'b0101: ALUctr = 3'b001;4'b0110: ALUctr = 3'b010;4'b011

23、1: ALUctr = 3'b011;4'b1000: ALUctr = 3'b100;4'b1001: ALUctr = 3'b100;4'b1010: ALUctr = 3'b100;4'b1011: ALUctr = 3'b100;default: ALUctr = 3'b111;endcase endmodule module alladd(A,B,Cin,Result_f,Carry_f,Zero,Overflow,Sign);input 31:0A;input 31:0B;input Cin;outpu

24、t 31:0Result_f;output Carry_f,Zero,Overflow,Sign;wire 31:0C;add f0(A0,B0,Cin,Result_f0,C0);add f1(A1,B1,C0,Result_f1,C1);add f2(A2,B2,C1,Result_f2,C2);add f3(A3,B3,C2,Result_f3,C3);add f4(A4,B4,C3,Result_f4,C4);add f5(A5,B5,C4,Result_f5,C5);add f6(A6,B6,C5,Result_f6,C6);add f7(A7,B7,C6,Result_f7,C7)

25、;add f8(A8,B8,C7,Result_f8,C8);add f9(A9,B9,C8,Result_f9,C9);add f10(A10,B10,C9,Result_f10,C10);add f11(A11,B11,C10,Result_f11,C11);add f12(A12,B12,C11,Result_f12,C12);add f13(A13,B13,C12,Result_f13,C13);add f14(A14,B14,C13,Result_f14,C14);add f15(A15,B15,C14,Result_f15,C15);add f16(A16,B16,C15,Resu

26、lt_f16,C16);add f17(A17,B17,C16,Result_f17,C17);add f18(A18,B18,C17,Result_f18,C18);add f19(A19,B19,C18,Result_f19,C19);add f20(A20,B20,C19,Result_f20,C20);add f21(A21,B21,C20,Result_f21,C21);add f22(A22,B22,C21,Result_f22,C22);add f23(A23,B23,C22,Result_f23,C23);add f24(A24,B24,C23,Result_f24,C24);

27、add f25(A25,B25,C24,Result_f25,C25);add f26(A26,B26,C25,Result_f26,C26);add f27(A27,B27,C26,Result_f27,C27);add f28(A28,B28,C27,Result_f28,C28);add f29(A29,B29,C28,Result_f29,C29);add f30(A30,B30,C29,Result_f30,C30);add f31(A31,B31,C30,Result_f31,C31);assign Carry_f = C31;assign Sign = Result_f31;as

28、sign Overflow = C30C31;assign Zero = (Result_f0|Result_f1|Result_f2|Result_f3|Result_f4|Result_f5|Result_f6|Result_f7|Result_f8|Result_f9|Result_f10|Result_f11|Result_f12|Result_f13|Result_f14|Result_f15|Result_f16|Result_f17|Result_f18|Result_f19|Result_f20|Result_f21|Result_f22|Result_f23|Result_f

29、24|Result_f25|Result_f26|Result_f27|Result_f28|Result_f29|Result_f30|Result_f31);endmodulemodule add(Xi,Yi,Ci_1,Fi,Ci);input Xi,Yi,Ci_1;output Fi,Ci;assign Fi=XiYiCi_1;assign Ci=(Xi&Ci_1) | (Yi&Ci_1) | (Xi&Yi);endmodulemodule mux32_6to1(x0,x1,x2,x3,x4,x5,ctr,R);input 31:0x0;input 31:0x1;

30、input 31:0x2;input 31:0x3;input 31:0x4;input 31:0x5;input 2:0ctr;output reg31:0R;always(ctr or x0 or x1 or x2 or x3 or x4 or x5)case(ctr)3'b000:R=x0;3'b001: R=x1;3'b010: R=x2;3'b011: R=x3;3'b100: R=x4;3'b101: R=x5;default R=32'b00000000000000000000000000000000;endcaseendm

31、odulemodule mux_4to1(A,B,C,D,ctr,R);input A,B,C,D;input 1:0ctr;output reg R;always(ctr or A or B or C or D)if (ctr = 2'b00)R = A;else if (ctr = 2'b01)R = B;else if (ctr = 2'b10)R = C;else / ctr = 2'b11R = D;endmodulemodule larger1to32(x1,x32);input x1;output reg31:0x32;always(x1)if (

32、x1=0)x32 = 32'b00000000000000000000000000000000;elsex32 = 32'b11111111111111111111111111111111;endmodulemodule ARM_move(D, S, ctr_LRAL, ctr_RRX, Q,in_C, C);input31:0 D; / datainput4:0 S; / number of transportinput1:0 ctr_LRAL; / circle shift right: 11 (ROR)/ shift right arithmetic: 01 (ASR)/

33、 shift left logical: 10 (LSL)/ shift right logical: 00 (LSR)input ctr_RRX; / RRX:1input in_C; / carryoutput31:0 Q; / resultoutput reg C; / carryreg31:0 q;reg1:0 w2;reg3:0 w4;reg7:0 w8;reg15:0 w16;reg temp;always(ctr_LRAL or ctr_RRX or D or S or in_C)beginq=D; temp=0; w2=0; w4=0; w8=0; w16=0;C=in_C;i

34、f (ctr_RRX=1)begintemp=q0;q30:0=q31:1;q31=in_C;C=temp;endelse if (ctr_LRAL1:0=2'b11) / RORbeginif (S0=1)begin temp=q0; q30:0=q31:1; q31=temp; end;if (S1=1)begin w2=q1:0; q29:0=q31:2; q31:30=w2; end;if (S2=1)begin w4=q3:0; q27:0=q31:4; q31:28=w4; end;if (S3=1)begin w8=q7:0; q23:0=q31:8; q31:24=w8

35、; end;if (S4=1)begin w16=q15:0; q15:0=q31:16; q31:16=w16; end;endelse if (ctr_LRAL1:0=2'b01) /shift right arithmetic (ASR)beginif (q31=1)beginw2=2'b11;w4=4'b1111;w8=8'b11111111;w16=16'b1111111111111111;endif (S0=1)begin q29:0=q30:1; q30=q31; end;if (S1=1)begin q28:0=q30:2; q30:29

36、=w2; end;if (S2=1)begin q26:0=q30:4; q30:27=w4; end;if (S3=1)begin q22:0=q30:8; q30:23=w8; end;if (S4=1)begin q14:0=q30:16; q30:15=w16; end;q31=D31;endelse if (ctr_LRAL1:0=2'b10) / shift left logical(LSL)beginif (S0=1)begin q31:1=q30:0; q0=0; end;if (S1=1)begin q31:2=q29:0; q1:0=2'b00; end;i

37、f (S2=1)begin q31:4=q27:0; q3:0=4'b0000; end;if (S3=1)begin q31:8=q23:0; q7:0=8'b00000000; end;if (S4=1)begin q31:16=q15:0; q15:0=16'b0000000000000000; end;endelse / shift right logical(LSR)beginif (S0=1)begin q30:0=q31:1; q31=0; end;if (S1=1)begin q29:0=q31:2; q31:30=2'b00; end;if (

38、S2=1)begin q27:0=q31:4; q31:28=4'b0000; end;if (S3=1)begin q23:0=q31:8; q31:24=8'b00000000; end;if (S4=1)begin q15:0=q31:16; q31:16=16'b0000000000000000; end;endendassign Q=q;endmodulemodule mux_2to1(A,B,ctr,R);input A,B,ctr;output reg R;always(ctr or A or B)if (ctr = 0)R = A;elseR = B;e

39、ndmodulemodule test_all0(in_32, out_1);input 31:0in_32;output reg out_1;always(in_32)if (in_32 = 32'b00000000000000000000000000000000)out_1 = 1;else out_1 = 0;endmodule3、仿真結(jié)果功能仿真:其中Result部分結(jié)果為：仿真結(jié)果說明：(為方便說明，ctr_LRAL, ctr_RRX, S均設(shè)置為0)AluOp功能Operand_AOperand_BC_before_moveResultCarryZeroOverflowLe

40、ss0000加法00000000000000000000000000001011000000000000000000000000000000010000000000000000000000000000000110000000001帶進(jìn)位的加法000000000000000000000000000010110000000000000000000000000000000100000000000000000000000000000110000000001帶進(jìn)位的加法00000000000000000000000000001011000000000000000000000000000000011000

41、0000000000000000000000000110100000010減法000000000000000000000000000010110000000000000000000000000000000100000000000000000000000000000101000000011帶進(jìn)位的減法000000000000000000000000000010110000000000000000000000000000000100000000000000000000000000000101000000011帶進(jìn)位的減法000000000000000000000000000010110000000000000000000000000000000110000000000000000000000000000100100000100位清除000000000000000000000000000010110000000000000000000000000000000100000000000000000000000000000101000000101與00000000000000000000000000001011000000000000000000000000000000010000000000000000000000000000000