五級流水CPU 帶冒險、轉(zhuǎn)發(fā)與分支

1、module ALU(aluControl,a,b,result,zero); input3:0 aluControl; input31:0 a,b; output zero; output31:0 result; reg31:0 result; always (aluControl or a or b) begin case(aluControl) 4'b0000: result=a&b; 4'b0001: result=a|b; 4'b0010: result=a+b; 4'b0110: result=a-b; 4'b0111: result

2、= (a<b)? 1:0; default: result=a+b; endcase end assign zero=(result=0) ? 1 : 0; endmodulemodule ALUcontrol (aluop,funct,aluControl);input 1:0aluop;input 5:0funct;output reg3:0aluControl;always(*)begincase (aluop)2'b00: aluControl<=4'b0010;2'b01: aluControl<=4'b0110;2'b10:

3、begincase (funct)6'b100000: aluControl<=4'b0010;6'b100010: aluControl<=4'b0110;6'b100100: aluControl<=4'b0000;6'b100101: aluControl<=4'b0001;6'b101010: aluControl<=4'b0111;default : aluControl<=4'b0010;endcaseenddefault : aluControl<=4

4、'b0010;endcaseendendmodulemodule controlUnit(stall,instruction,RegDst,Jump,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUsrc,RegWrite);input 5:0instruction;input stall;/stall=1時表示沒有發(fā)生堵塞;output reg RegDst;output reg Jump;output reg Branch;output reg MemRead;output reg MemtoReg;output reg1:0ALUOp;outp

5、ut reg MemWrite;output reg ALUsrc;output reg RegWrite;initialbeginRegDst=1;ALUsrc=0;MemtoReg=0;RegWrite=0;MemRead=0;MemWrite=0;Branch=0;ALUOp1=1;ALUOp0=0;Jump=1;endalways(*)beginif(stall)begincase (instruction)6'b000000:/R typebeginRegDst=1;ALUsrc=0;MemtoReg=0;RegWrite=1;MemRead=0;MemWrite=0;Bra

6、nch=0;ALUOp1=1;ALUOp0=0;Jump=1;end6'b001000:/addibeginRegDst=0;ALUsrc=1;MemtoReg=0;RegWrite=1;MemRead=0;MemWrite=0;Branch=0;ALUOp1=0;ALUOp0=0;Jump=1;end6'b100011:/lwbeginRegDst=0;ALUsrc=1;MemtoReg=1;RegWrite=1;MemRead=1;MemWrite=0;Branch=0;ALUOp1=0;ALUOp0=0;Jump=1;end 6'b101011:/swbeginA

7、LUsrc=1;RegWrite=0;MemRead=0;MemWrite=1;Branch=0;ALUOp1=0;ALUOp0=0;Jump=1;end 6'b000100:/beqbeginALUsrc=0;RegWrite=0;MemRead=0;MemWrite=0;Branch=1;ALUOp1=0;ALUOp0=1;Jump=1;end 6'b000010:/j beginJump=0;enddefault:beginRegDst=0;ALUsrc=0;MemtoReg=0;RegWrite=0;MemRead=0;MemWrite=0;Branch=0;ALUOp

8、1=1;ALUOp0=0;Jump=1;endendcaseend else begin/阻塞RegDst=0;ALUsrc=0;MemtoReg=0;RegWrite=0;MemRead=0;MemWrite=0;Branch=0;ALUOp1=1;ALUOp0=0;Jump=1;endendendmodulemodule dm_4k( addr, din, we, re,clk, dout ) ; input 11:2 addr ; / address bus input 31:0 din ; / 32-bit input data input we ; / memory write en

9、able input re; /memory read enable input clk; / clock output reg31:0 dout ; / 32-bit memory output reg 31:0 dm1023:0 ; integer i; initial begin for ( i = 0; i < 1024; i=i+1) begin dmi<=32'b0000_0000_0000_0000_0000_0000_0000_0000; end dout=0; end always (posedge clk) begin if (we) begin dma

10、ddr11:231:0 <= din31:0; end if (re) begin dout31:0 <= dmaddr11:231:0; end endendmodulemodule EXMEM_reg (clk,wb,m,mux_result,add_result,zero_flag,alu_result,out_toMux,out_wb,branch,memRead,memWrite,out_mux_result,zero,out_toPCmux,out_address,out_writeData);input clk; input 1:0 wb; input 2:0 m;

11、input 4:0 mux_result;input 31:0add_result;input zero_flag;input 31:0alu_result;input 31:0out_toMux;output 1:0out_wb;output branch;output memRead;output memWrite;output 4:0out_mux_result;output zero;output 31:0out_toPCmux;output 31:0out_address;output 31:0out_writeData;reg106:0EXMEM_register;integer

12、i;initialbeginfor ( i = 0; i < 107; i=i+1) beginEXMEM_registeri<=1'b0;endendalways(posedge clk)beginEXMEM_register106:105<=wb;EXMEM_register104:102<=m;EXMEM_register101:97<=mux_result;EXMEM_register96<=zero_flag;EXMEM_register95:64<=add_result;EXMEM_register63:32<=alu_res

13、ult;EXMEM_register31:0<=out_toMux;endassignout_wb=EXMEM_register106:105;assignbranch=EXMEM_register104;assignmemRead=EXMEM_register103;assignmemWrite=EXMEM_register102;assignout_mux_result=EXMEM_register101:97;assign zero=EXMEM_register96;assignout_toPCmux=EXMEM_register95:64;assignout_address=EX

14、MEM_register63:32;assignout_writeData=EXMEM_register31:0;endmodulemodule SigExtend(origin,ext_result);parameter tem_WIDTH=16; inputtem_WIDTH-1:0 origin; output31:0 ext_result; assign ext_result=(32-tem_WIDTH)origintem_WIDTH-1,origin;endmodule module forwardUnit (exmem_registerRd,memwb_registerRd,ide

15、x_registerRs,idex_registerRt,exmem_regwrite,memwb_regwrite,forwardA,forwardB);input 4:0 exmem_registerRd;input 4:0 memwb_registerRd;input 4:0 idex_registerRs;input 4:0 idex_registerRt;input exmem_regwrite;input memwb_regwrite;output reg1:0 forwardA;output reg1:0 forwardB;always(*)beginif(exmem_regwr

16、ite && (exmem_registerRd!=0) && (exmem_registerRd=idex_registerRs) beginforwardA1=1;forwardA0=0;end else if(memwb_regwrite && (memwb_registerRd!=0)&& !(exmem_regwrite &&(exmem_registerRd!=0) &&(exmem_registerRd=idex_registerRs) &&(memwb_registe

17、rRd=idex_registerRs) beginforwardA1=0;forwardA0=1;end else beginforwardA1=0;forwardA0=0;end if (exmem_regwrite && (exmem_registerRd!=0) && (exmem_registerRd=idex_registerRt)beginforwardB1=1;forwardB0=0;endelse if (memwb_regwrite &&(memwb_registerRd!=0)&& !(exmem_regwr

18、ite &&(exmem_registerRd!=0)&&(exmem_registerRd!=idex_registerRt) && (memwb_registerRd=idex_registerRt)beginforwardB1=0;forwardB0=1;endelse beginforwardB1=0;forwardB0=0;endendendmodulemodule IDEX_reg (clk,wb_signals,m_signals,ex_signals,out_pc_plus4,rdata1,rdata2,extend_data,i

19、ns_part1,ins_part2,ins_part3,out_toWb,out_toM,RegDst,ALUop,AluSrc,out_toAdd,out_toALU0,out_toMUX,out_extend,out_ins_part1,out_ins_part2,out_ins_part3);input clk;input 1:0 wb_signals;input 2:0 m_signals;input 3:0 ex_signals;input 31:0out_pc_plus4;input 31:0rdata1;input 31:0rdata2;input 31:0extend_dat

20、a;/newinput 4:0 ins_part1; input 4:0 ins_part2; input 4:0 ins_part3; output 1:0 out_toWb; output 2:0 out_toM; output RegDst; output 1:0 ALUop; output AluSrc;output 31:0out_toAdd;output 31:0out_toALU0;output 31:0out_toMUX;output 31:0out_extend;output 4:0 out_ins_part1;output 4:0 out_ins_part2;output

21、4:0 out_ins_part3;reg 4:0rs;reg146:0 IDEX_register;integer i;initialbeginfor ( i = 0; i < 147; i=i+1) beginIDEX_registeri <=1'b0;endrs4:0=0;endalways(posedge clk)beginrs4:0<=ins_part1;IDEX_register146:145<=wb_signals;IDEX_register144:142<=m_signals;IDEX_register141:138<=ex_sign

22、als;IDEX_register137:133<=ins_part2;IDEX_register132:128<=ins_part3;IDEX_register127:96<=out_pc_plus4;IDEX_register95:64<=rdata1;IDEX_register63:32<=rdata2;IDEX_register31:0<=extend_data;endassign out_ins_part1=rs4:0;assignout_toWb=IDEX_register146:145;assignout_toM=IDEX_register14

23、4:142; assign RegDst=IDEX_register141; assign ALUop=IDEX_register140:139; assign AluSrc=IDEX_register138;assignout_ins_part2=IDEX_register137:133;assignout_ins_part3=IDEX_register132:128;assignout_toAdd=IDEX_register127:96;assignout_toALU0=IDEX_register95:64;assignout_toMUX=IDEX_register63:32;assign

24、out_extend=IDEX_register31:0;endmodulemodule IFID_reg (stall,flush,clk,rst,pc_plus4,dout,out_pc_plus4,out_instruction);input stall;/stall=1時表示沒有發(fā)生堵塞input flush;/flush=1時表示有效input clk;input rst;input31:0 pc_plus4;input31:0 dout;output 31:0out_pc_plus4;output 31:0out_instruction;reg63:0 IFID_register;

25、integer i;initial beginfor ( i = 0; i < 64; i=i+1) beginIFID_registeri<=1'b0;end endalways(posedge clk)beginif(rst) for ( i = 0; i < 64; i=i+1) begin IFID_registeri<=1'b0; endif(flush)beginIFID_register63:32<=pc_plus4;IFID_register31:0<=32'h0000; end else if(stall)begin

26、 IFID_register63:32<=pc_plus4; IFID_register31:0<=dout;endendassignout_pc_plus431:0=IFID_register63:32;assignout_instruction31:0=IFID_register31:0;endmodulemodule im_4k( addr, dout ) ;input11:2addr ; / address busoutput31:0dout ; / 32-bit memory outputreg31:0im1023:0 ;initialbegin$readmemh(&qu

27、ot;code.txt", im);endassign dout = imaddr11:231:0;endmodulemodule maoxianDetectUnit (idex_memread,idex_registerRt,ifid_registerRs,ifid_registerRt,stall);input idex_memread;input 4:0idex_registerRt;input 4:0ifid_registerRs;input 4:0ifid_registerRt;output reg stall;/stall=1時表示沒有發(fā)生堵塞initial begins

28、tall=1;end always(*) beginif(idex_memread && (idex_registerRt=ifid_registerRs) | (idex_registerRt=ifid_registerRt)begin stall=0;endelse begin stall=1;end endendmodulemodule MEMWB_reg (clk,wb,mux_result,in_rdata,in_address,regWrite,memToReg,writeReg,mux0,mux1);input clk;input 1:0 wb;input 4:0

29、 mux_result;input31:0 in_rdata;input31:0 in_address;output regWrite;output memToReg;output 4:0 writeReg;output 31:0mux0;output 31:0mux1;reg70:0 MEMWB_register;integer i;initialbeginfor ( i = 0; i < 71; i=i+1) beginMEMWB_registeri <=1'b0;endendalways(posedge clk)beginMEMWB_register70:69<

30、=wb;MEMWB_register68:64<=mux_result;MEMWB_register63:32<=in_rdata;MEMWB_register31:0<=in_address;endassignregWrite=MEMWB_register70;assignmemToReg=MEMWB_register69;assignwriteReg=MEMWB_register68:64;assignmux031:0=MEMWB_register63:32;assignmux131:0=MEMWB_register31:0;endmoduleinclude "

31、ctrl.v"include "ALUcontrol.v"include "alu.v"include "dm.v"include "im.v"include "mux.v"include "pc.v"include "rf.v"include "IFID_reg.v"include "IDEX_reg.v"include "EXMEM_reg.v"include "MEMWB

32、_reg.v"include "extend.v"include "maoxianDetectUnit.v"include "forwardUnit.v"module mips(clk, rst);input clk ; / clockinput rst ;/ resetwire31:0cur_pc;wire31:0 pcAlu_result;wire31:0next_pc;wire31:0 pc_plus4;wire31:0 branch_mux_result;wire31:0instruction;wire4:0wreg

33、;wire31:0rdata1;wire31:0rdata2;wire31:0 extend;wire zero;wire31:0rdata;wire31:0wdata;wire3:0alucontr;wire RegDst;wire Jump;wire Branch;wire MemRead;wire MemtoReg;wire1:0alu_op;wire MemWrite;wire ALUSrc;wire RegWrite; /new wires wire 31:0 if_id_pc_plus4; wire 31:0 out_instruction; wire 31:0 id_ex_out

34、_extend;wire RegDst_idex;wire Branch_idex;wire MemRead_idex;wire MemtoReg_idex;wire1:0alu_op_idex;wire MemWrite_idex;wire ALUsrc_idex; wire RegWrite_idex;wire4:0mux_result;wire 1:0wb_ex;wire 2:0m_ex;wire 31:0toAdd;wire 31:0out_to_mux;wire 31:0out_to_alu0;wire 4:0regdst_mux0;wire 4:0regdst_mux1;wire

35、zero_flag;wire31:0alu_result;wire1:0wb_mem;wire31:0out_toPCmux;wire4:0out_mux_result;wire31:0out_address;wire31:0out_writeData;wire31:0in_rdata;wire 31:0regsrc_mux1;/forward new addwire1:0forwardA;wire1:0forwardB;wire 31:0forwardToAlu0;wire 31:0forwardToAlu1;wire 31:0alusrc_mux_0;wire 4:0 rs;wire st

36、all;/stall=1時表示沒有發(fā)生堵塞;/brunch new addwire equel;wire flush;/flush=1時表示有效assign pc_plus4=cur_pc+4;MUX32_2_1 #(32) brunch_mux(.A(pc_plus4), .B(pcAlu_result), .sel(flush), .result(branch_mux_result);MUX32_2_1 #(32) jump_mux(.A(pc_plus431:28,out_instruction25:0,2'b00), .B(branch_mux_result),.sel(Jum

37、p), .result(next_pc);im_4k myIM(.addr(cur_pc11:2),.dout(instruction);PC myPc(.stall(stall),.clk(clk),.rst(rst),.address(next_pc),.out(cur_pc);SigExtend ext(.origin(out_instruction15:0),.ext_result(extend); IFID_reg ifid(.stall(stall),.flush(flush),.clk(clk),.rst(rst), .pc_plus4(pc_plus4),.dout(instr

38、uction),.out_pc_plus4(if_id_pc_plus4), .out_instruction(out_instruction);controlUnit myCunit(.stall(stall),.instruction(out_instruction31:26),.RegDst(RegDst_idex),.Jump(Jump),.Branch(Branch_idex),.MemRead(MemRead_idex),.MemtoReg(MemtoReg_idex),.ALUOp(alu_op_idex),.MemWrite(MemWrite_idex),.ALUsrc(ALU

39、src_idex),.RegWrite(RegWrite_idex); assign flush=Branch_idex&&equel; IDEX_reg idex(.clk(clk),.wb_signals(RegWrite_idex,MemtoReg_idex), .m_signals(Branch_idex,MemRead_idex,MemWrite_idex), .ex_signals(RegDst_idex,alu_op_idex,ALUsrc_idex), .out_pc_plus4(if_id_pc_plus4),.rdata1(rdata1),.rdata2(r

40、data2), .extend_data(extend),.ins_part1(out_instruction25:21), .ins_part2(out_instruction20:16),.ins_part3(out_instruction15:11), .out_toWb(wb_ex),.out_toM(m_ex),.RegDst(RegDst),.ALUop(alu_op), .AluSrc(ALUSrc),.out_toAdd(toAdd),.out_toALU0(out_to_alu0), .out_toMUX(out_to_mux),.out_extend(id_ex_out_e

41、xtend),.out_ins_part1(rs), .out_ins_part2(regdst_mux0),.out_ins_part3(regdst_mux1);MUX32_2_1 #(32)alu_src(.A(alusrc_mux_0),.B(id_ex_out_extend),.sel(ALUSrc),.result(forwardToAlu1);ALUcontrol myALUcontr(.aluop(alu_op),.funct(id_ex_out_extend5:0),.aluControl(alucontr);ALU myALU(.aluControl(alucontr),.

42、a(forwardToAlu0),.b(forwardToAlu1),.result(alu_result),.zero(zero_flag);ALU pc_alu(.aluControl(4'b0010), .a(if_id_pc_plus4), .b(extend29:0, 2'b00), .result(pcAlu_result);/無zero輸出端MUX32_2_1 #(5)writeReg_mux(.A(regdst_mux0),.B(regdst_mux1),.sel(RegDst),.result(mux_result);EXMEM_reg exmem(.clk(

43、clk),.wb(wb_ex),.m(m_ex),.mux_result(mux_result),.add_result(pcAlu_result),.zero_flag(zero_flag),.alu_result(alu_result),.out_toMux(alusrc_mux_0),.out_wb(wb_mem),.branch(Branch),.memRead(MemRead),.memWrite(MemWrite),.out_mux_result(out_mux_result),.zero(zero),.out_toPCmux(out_toPCmux),.out_address(o

44、ut_address),.out_writeData(out_writeData); MEMWB_reg memwb(.clk(clk),.wb(wb_mem),.mux_result(out_mux_result), .in_rdata(in_rdata),.in_address(out_address),.regWrite(RegWrite), .memToReg(MemtoReg),.writeReg(wreg),.mux0(rdata),.mux1(regsrc_mux1);MUX32_2_1 #(32) regSrc(.A(regsrc_mux1),.B( rdata),.sel(M

45、emtoReg),.result(wdata); dm_4k myDM(.clk(clk),.addr(out_address),.din(out_writeData), .we(MemWrite),.re(MemRead),.dout(in_rdata);RegFile myRF(.clk(clk),.we3(RegWrite),.ra1(out_instruction25:21),.ra2(out_instruction20:16),.wa3(wreg),.data(wdata),.rd1(rdata1),.rd2(rdata2);assign equel=(rdata1=rdata2)?

46、1:0;MUX32_3_1 #(32) forw_A_mux (.A(out_to_alu0), .C(out_address), .B( wdata), .sel(forwardA), .result(forwardToAlu0);MUX32_3_1 #(32) forw_B_mux (.A(out_to_mux), .C(out_address),.B( wdata), .sel(forwardB), .result(alusrc_mux_0); forwardUnit myForwardUnit(.exmem_registerRd(mux_result), .memwb_registerRd(out_mux_result),.idex_registerRs(rs), .idex_registerRt(regdst_mux0),.exmem_regwrite(wb_mem1), .memwb_regwrite(RegWrite),.forwardA(forwardA),.forwardB(forwardB);maoxianDetectUnit mymdu(.idex_memread(m_ex1),.idex_registerRt(regdst_mux0),.ifid_registerRs