微程序控制器試驗報告

1、一、實驗目的1、通過實驗，進一步理解微程序控制器的組成結(jié)構(gòu)。理解微程序控制器的控制原理2、加深理解微程序控制器的工作原理。掌握指令流程與功能3、理解掌握微程序控制器的設計思路與方法二、實驗內(nèi)容與步驟1、微程序控制器的組成原理控制存儲器：實現(xiàn)整個指令系統(tǒng)的所有微程序，一般指令系統(tǒng)是規(guī)定的由高速半導體存儲器構(gòu)成， 容量視機器指令系統(tǒng)而定，取決于微程序的個數(shù)，其長度就是微指令字的長度。微指令寄存器：存放從控存讀出的當前微指令。微操作控制字段將操作控制信號送到控制信號線上，微地址字段指出下一條微地址的形成。微地址寄存器：存放將要訪問的下一條微指令地址地址轉(zhuǎn)移邏輯：形成將要執(zhí)行的微指令地址，形成方式：取

2、指令公操作所對應的微程序一般從控存的0地址開始，所以微程序的人口地址0是由硬件控制的。當出現(xiàn)分支時，通過判別測試字段、微地址字段、和執(zhí)行部件的反饋信息形成后即微地址。Cpu設計步驟：1. 擬定指令系統(tǒng)2. 確定總體結(jié)構(gòu)（數(shù)據(jù)通路）3. 安排時序4. 擬定指令流程。根據(jù)指令系統(tǒng)，寫出對應所有機器指令的全部微操作機器節(jié)拍安排，然后列出 操作時間表5. 確定微指令的控制方式、下地址形成方式、微指令格式及微指令字長，編寫全部的微指令的代 碼，最后將編寫的微指令放入控制存儲器中。微程序控制器的設計步驟（1）設計微程序 確定微程序流程圖，也就是控制算法流程圖。（2 ）確定微指令格式微指令格式中的操作控制字

3、段取決于執(zhí)行部件的子系統(tǒng)需要多少微指令。假定采用直接控制方 式，執(zhí)行部件需要 10個微命令，則操作控制字段需要10位。測試判別字段取決于微程序流程圖中有多少處分支轉(zhuǎn)移。假定有3處分支，則測試判別字段需要3位。下址字段取決于微程序流程圖的規(guī)模。假定微程序共用50條微指令，則下址字段至少需要6位。這是因為ROM地址譯碼時，26=64，6位地址可容納64條微指令。（3）將微程序編譯成二進制代碼（4 ）微程序?qū)懭肟刂拼鎯ζ?5)設計硬件電路三、實驗現(xiàn)象-CPU 頭文件 cpu_defsLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE cpu_defs I

4、S-定義程序包，包頭，包體TYPEopcode IS (load, store, add, sub, bne); -這個語句適合于定義一些用std_logic 等不方便定義的類型，綜合器自動實現(xiàn)枚舉類型元素的編碼，一般將第一個枚舉量(最左邊)編碼為 0CONSTANT word_w: NATURAL :=8;CONSTANT op_w: NATURAL :=3;CONSTANT rfill: STD_LOGIC_VECTOR(op_w-1 downto 0):=(others =>'0');-FUNCTIOn slv2op(slv:IN STD_LOGIC_VECTOR)

5、 RETURN opcode;FUNCTION op2slv(op:in opcode) RETURN STD_LOGIC_VECTOR;END PACKAGE cpu_defs;PACKAGE BODY cpu_defs ISTYPEoptable IS ARRAY(opcode) OF STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);- 數(shù)組有 5 個元素，其他均 0CONSTANT trans_table:optable :=("000", "001", "010", "011", &qu

6、ot;100");FUNCTION op2slv(op:IN opcode) RETURN STD_LOGIC_VECTOR ISBEGINRETURN trans_table(op);END FUNCTION op2slv;END PACKAGE BODY cpu_defs;-實驗 7-8 微程序控制器實驗LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;USE WORK.CPU_DEFS.ALL;- 使用自己定義的程序包ENTITY CPU ISPORT( clock: IN STD_LOGIC;- 時鐘-

7、查看用reset : INSTD_LOGIC;- 復位mode: INSTD_LOGIC_VECTOR(2 DOWNTO 0);mem_addr : INUNSIGNED(word_w-op_w-1 DOWNTO 0);- 地址 output : OUT STD_LOGIC_VECTOR(word_w-1 DOWNTO 0); data_r_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);- 微指令 R op_out: OUT STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);- 操作碼add_r_out : OUT UNSIGNED(4 DO

8、WNTO 0)-微地址 R);END ENTITY;ARCHITECTURE rtl OF CPU ISTYPE mem_array IS ARRAY (0 TO 2*(word_w-op_w)-1) OF STD_LOGIC_VECTOR(word_w-1DOWNTO 0);- 定義 RAMSIGNAL mem : mem_array;CONSTANT prog : mem_array:=(0=> op2slv(load) & STD_LOGIC_VECTOR(TO_UNSIGNED(4,word_w-op_w),1=> op2slv(add) & STD_LOG

9、IC_VECTOR(TO_UNSIGNED(5,word_w-op_w),2=> op2slv(store) & STD_LOGIC_VECTOR(TO_UNSIGNED(6,word_w-op_w),3=> op2slv(bne) & STD_LOGIC_VECTOR(TO_UNSIGNED(7,word_w-op_w),-TO_UNSIGNED 轉(zhuǎn)換函數(shù)將 4 轉(zhuǎn)換為 5 位“ 00100 ”4=> STD_LOGIC_VECTOR(TO_UNSIGNED(2,word_w),5=> STD_LOGIC_VECTOR(TO_UNSIGNED(3,wo

10、rd_w),OTHERS => (OTHERS =>'0');TYPE microcode_array IS ARRAY (0 TO 14) OF STD_LOGIC_VECTOR(19 DOWNTO 0);CONSTANT code: microcode_array:=(- 控制存儲器0=> "00010100010000000001",1=> "00000000000110000010",2=> "00001010000000000011",3=> "000001000

11、01000001111",4=> "00100010000000000000",5=> "00000000000100000000",6=> "00000010100001000000",7=> "00000010100000100000",8=> "00000000000110000100",9=> "01000001000000000101", 10=> "00000000000110000110",

12、11=> "00000000000110000111", 12=> "00000000000110010000",13=> "10000010000000000000",14=> "00000000000000000000");SIGNAL countSIGNAL opSIGNAL z_flagSIGNAL mdr_outSIGNAL mar_outSIGNAL IR_outSIGNAL acc_out: UNSIGNED(word_w-op_w-1 DOWNTO 0);: STD_LOGI

13、C_VECTOR(op_w-1 DOWNTO 0);: STD_LOGIC;: STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);: UNSIGNED(word_w-op_w-1 DOWNTO 0);: STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);: UNSIGNED(word_w-1 DOWNTO 0);SIGNAL sysbus_out : STD_LOGIC_VECTOR(word_w-1 DOWNTO 0); EGINPROCESS(reset,clock)VARIABLE instr_reg : STD_LOGIC_VECTOR(wo

14、rd_w-1 DOWNTO 0);VARIABLE acc CONSTANT zero VARIABLE mdr VARIABLE marVARIABLE sysbus: UNSIGNED(word_w-1 DOWNTO 0);: UNSIGNED(word_w-1 DOWNTO 0):=(OTHERS =>'0'): STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);: UNSIGNED(word_w-op_w-1 DOWNTO 0);: STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);VARIABLE microcode

15、: microcode_array;VARIABLE add_r : UNSIGNED(4 DOWNTO 0);VARIABLE data_r: STD_LOGIC_VECTOR(19 DOWNTO 0);VARIABLE temp : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGINIF reset='0' THENadd_r:=(OTHERS =>'0');count<= (OTHERS =>'0');instr_reg := (OTHERS =>'0');acc:= (OTHER

16、S =>'0');mdr:= (OTHERS =>'0');mar:= (OTHERS =>'0');z_flag <='0'mem <= prog;sysbus :=(OTHERS =>'0');ELSIF RISING_EDGE(clock) THEN-microprogram controllerdata_r := code(TO_INTEGER(add_r);IF data_r(4 DOWNTO 0)="01111" THEN - 判斷下地址 temp

17、:="01" & op(2 DOWNTO 0); add_r := UNSIGNED(temp);ELSIF data_r(4 DOWNTO 0)="10000" THENIF z_flag='1' THEN add_r:="01110"ELSEadd_r :="01101"END IF;ELSEadd_r := UNSIGNED(data_r(4 DOWNTO 0);END IF;data_r_out <=data_r; add_r_out <= add_r;-PCIF dat

18、a_r(16)='1' THEN-PC_bus='1'sysbus := rfill & STD_LOGIC_VECTOR(count);END IF;IF data_r(19)='1' THEN-load_PC='1'count <= UNSIGNED(mdr(word_w-op_w-1 DOWNTO 0);ELSIF data_r(10)='1' THEN-INC_PC='1'count <= count+1;ELSEcount <= count;END IF;-IRI

19、F data_r(15)='1' THEN-load_IRinstr_reg := mdr;END IF;IF data_r(9)='1' THEN-Addr_bus='1'sysbus := rfill & instr_reg(word_w-op_w-1 DOWNTO 0);END IF;op <= instr_reg(word_w-1 DOWNTO word_w-op_w); IR_out <= instr_reg;-ALUop_out <=op;IF data_r(17)='1' THEN-load

20、_ACC='1'acc:=UNSIGNED(mdr);END IF;IF data_r(11)='1' THEN -ALU_ACC='1'IF data_r(6)='1' THEN-ALU_add='1'acc := acc + UNSIGNED(mdr);ELSIF data_r(5)='1' THEN-ALU_sub='1'acc := acc - UNSIGNED(mdr);END IF;END IF;IF data_r(18)='1' THEN -ACC_bu

21、s='1' sysbus := STD_LOGIC_VECTOR(acc);END IF;IF acc=zero THEN z_flag <='1'ELSEz_flag <='0' END IF; acc_out<= acc;-RAMIF data_r(14)='1' THEN -load_MAR='1' mar := UNSIGNED(sysbus(word_w-op_w-1 DOWNTO 0);-load_MDR='1'-CS='1'-R_NW='1&#

22、39;ELSIF data_r(12)='1' THEN mdr := sysbus;ELSIF data_r(8)='1' THENIF data_r(7)='1' THENmdr := mem(TO_INTEGER(mar); ELSEmem(TO_INTEGER(mar)<=mdr;END IF;END IF;IF data_r(13)='1' THEN-MDR_bus='1'sysbus:=mdr;END IF;mdr_out <= mdr; mar_out <= mar;END IF; sysbus_out <=sysbus;END PROCESS; PROCESS(mode,mem_addr)BEGIN-mode=0 -> sysbus-mode=1 -> PC-mode=2 -> result of ALU-mode=3 -> IR-mode=4 -> MAR-mode=5 -> MDR-