異步、同步數(shù)據(jù)接口設(shè)計(jì)

1、異步數(shù)據(jù)接口設(shè)計(jì)一、設(shè)計(jì)要求1、輸入數(shù)據(jù)以學(xué)號(hào)重復(fù)循環(huán)組成， 學(xué)號(hào)的每一位以一個(gè)字節(jié) （8bit ） 表示，以字節(jié)串行方式，高位字節(jié)先輸入，低位字節(jié)后輸入。字節(jié)輸 入時(shí)鐘頻率30MHz頻率初始相位自定義。2、輸出數(shù)據(jù)：以字節(jié)串行方式輸出學(xué)號(hào)，高位字節(jié)先輸出，低位 字節(jié)后輸出。 學(xué)號(hào)的輸出必須連續(xù)不間斷地完整輸出一個(gè)學(xué)號(hào)， 相鄰 學(xué)號(hào)間可插入多個(gè)H“FF”字節(jié)。字節(jié)輸出時(shí)鐘頻率100MHz頻率初 始相位自定義。3、分別以同步FIFO和異步FIFO實(shí)現(xiàn)上述接口設(shè)計(jì)。完成硬件描 述語(yǔ)言設(shè)計(jì)、綜合、時(shí)序仿真驗(yàn)證。分別對(duì)以上兩種實(shí)現(xiàn)方案進(jìn)行性 能分析并比較各自的優(yōu)缺點(diǎn)。二、設(shè)計(jì)分析1、同步FIFO由同一

2、個(gè)時(shí)鐘控制FIFO的讀寫(xiě)操作，所以設(shè)計(jì)相對(duì) 簡(jiǎn)單，對(duì)于實(shí)現(xiàn)上述接口設(shè)計(jì)，可以簡(jiǎn)單劃分為讀控制單元、寫(xiě)控制 單元、數(shù)據(jù)轉(zhuǎn)存單元實(shí)現(xiàn)。其中讀控制單元為簡(jiǎn)單的邏輯控制單元， 主要用于產(chǎn)生讀信號(hào)， 寫(xiě)控制單元類(lèi)似于讀控制單元， 主要用于產(chǎn)生 寫(xiě)狀態(tài)信號(hào)，數(shù)據(jù)轉(zhuǎn)存單元主要由存儲(chǔ)器組成，當(dāng)寫(xiě)信號(hào)有效，將 8bit 的輸入數(shù)據(jù)寫(xiě)入存儲(chǔ)器（存儲(chǔ)器未滿情形下） ，當(dāng)讀信號(hào)有效， 從存儲(chǔ)器中讀出 8bit 的數(shù)據(jù)（存儲(chǔ)器未空情形下） 。結(jié)構(gòu)圖如圖 1 所示:d|elucM ns-sartlread cairrorizbGkreseiI< TillI嘰曲向 Qiiljull也時(shí) mo 刃欝 m ptyT 丄*

3、訂牡EmohrjHI3_WITT D|writ! Lu nil J U1圖1、同步FIFO的接口設(shè)計(jì)結(jié)構(gòu)圖2、異步FIFO分別利用讀時(shí)鐘和寫(xiě)時(shí)鐘控制 FIFO的讀寫(xiě)操作，因 為涉及到跨時(shí)鐘域設(shè)計(jì)，相對(duì)于同步 FIFO時(shí)序要復(fù)雜。如圖2結(jié)構(gòu) 圖所示，設(shè)計(jì)劃分為數(shù)據(jù)通道單元、控制單元、狀態(tài)控制單元。數(shù)據(jù) 通道單元類(lèi)似于數(shù)據(jù)轉(zhuǎn)存單元，控制數(shù)據(jù)的流入流出存儲(chǔ)器?？刂茊?元根據(jù)輸入產(chǎn)生讀寫(xiě)控制標(biāo)志，從而控制其他兩個(gè)模塊的讀寫(xiě)。狀態(tài) 控制單元主要用于產(chǎn)生標(biāo)志存儲(chǔ)器當(dāng)前狀態(tài)（空、滿等）的各個(gè)標(biāo)志 位，同時(shí)產(chǎn)生讀寫(xiě)時(shí)訪問(wèn)存儲(chǔ)器需要的指針。 其基本結(jié)構(gòu)圖如圖2所示:圖2、異步FIFO的接口設(shè)計(jì)結(jié)構(gòu)圖三、設(shè)計(jì)實(shí)現(xiàn)

4、1、基于上述同步FIFO接口設(shè)計(jì)的分析，分模塊對(duì)電路進(jìn)行HDL建模，HDLI苗述如下:(1) 讀操作控制模塊：module read_control (input clock,reset,input stk_empty, output reg read);always (posedge clock or posedge reset) if(reset) read<=1'b0;else if(!stk_empty) read<=1'b1;else read<=1'b0;endmodule(2) 寫(xiě)操作控制模塊:module write_control (

5、input clock,reset,input stk_full, output reg write );always (posedge clock or posedge reset) if(reset) write<=1'b0;else if(!stk_full)write<=1'b1;else write<=1'b0;endmodule(3) 數(shù)據(jù)轉(zhuǎn)換模塊:module fifo_syn #(parameter stk_width=8,half_stk_depth=8,stk_depth=16,ptr_width=4)(clock,reset,da

6、ta_in,write,read,data_out,stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty);input clock,reset,write,read;input stk_width-1:0 data_in;output stk_width-1:0 data_out;/reg stk_full,stk_almost_full,stk_half_full,stk_alm reg stk_width-1:0 data_out;reg ptr_width-1:0write_ptr,read_ptr;reg p

7、tr_width:0ptr_gap;reg stk_width-1:0stackstk_depth-1:0;assign stk_full=(ptr_gap=stk_depth)?1'b1:1'b0; assign stk_almost_full=(ptr_gap=(stk_depth-2)?1'b1:1'b0; assign stk_half_full=(ptr_gap=half_stk_depth)?1'b1:1'b0; assign stk_almost_empty=(ptr_gap=2)?1'b1:1'b0;assign

8、stk_empty=(ptr_gap=0)?1'b1:1'b0;always (posedge clock or posedge reset) if(reset)begin write_ptr<=1'b0; read_ptr<=1'b0; ptr_gap<=1'b0;endelsebegin if(write)&&(!stk_full)&&(!read) beginstackwrite_ptr<=data_in; write_ptr<=write_ptr+1'b1; ptr_gap&l

9、t;=ptr_gap+1'b1;endelse if(read)&&(!stk_empty)&&(!write) begindata_out<=stackread_ptr; read_ptr<=read_ptr+1'b1; ptr_gap<=ptr_gap-1'b1;endelse if(write)&&(read)&&(stk_full)&&(!stk_empty) begindata_out<=stackread_ptr; read_ptr<=read_pt

10、r+1'b1; ptr_gap<=ptr_gap-1'b1;endelse if(write)&&(read)&&(stk_empty)&&(!stk_full) beginstackwrite_ptr<=data_in; write_ptr<=write_ptr+1'b1; ptr_gap<=ptr_gap+1'b1;endelse if(write)&&(read)&&(!stk_full)&&(!stk_empty) beginstack

11、write_ptr<=data_in; write_ptr<=write_ptr+1'b1; data_out<=stackread_ptr; read_ptr<=read_ptr+1'b1;endendendmodule(4) 頂層例化：module top_fifo #(parameter stk_width=8) (clock,reset,data_in,data_out,stk_full,stk_almost_full,stk_half_full, stk_almost_empty,stk_empty);input clock,reset;inp

12、ut stk_width-1:0 data_in;output stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty;output stk_width-1:0 data_out;wire write_net,read_net;write_control U1(clock,reset,stk_full,write_net);read_control U2( clock,reset,stk_empty,read_net); fifo_synU3(clock,reset,data_in,write_net,read_net

13、,data_out,stk_full,stk_almost_full ,stk_half_full,stk_almost_empty,stk_empty);endmodule(5)testbench 模塊：'timescale 1ns/1nsmodule tb_top_fifo #(parameter stk_width=8);reg clock,reset;reg stk_width-1:0 data_in;wire stk_full,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty;wire stk_width-1:0

14、 data_out; top_fifoU(clock,reset,data_in,data_out,stk_full,stk_almost_full,stk_half_full, stk_almost_empty,stk_empty);initialbeginclock=0;reset=0;data_in=0;endalways #5 clock=clock;initialbegin#10 reset=1;#10 reset=0;endinitialbegin#20repeat(10)begin#10 data_in=8'd2;#10 data_in=8'd0;#10 data

15、_in=8'd1;#10 data_in=8'd3;#10 data_in=8'd2;#10 data_in=8'd2;#10 data_in=8'd2;#10 data_in=8'd4;#10 data_in=8'd0;#10 data_in=8'd2;#10 data_in=8'd3;#10 data_in=8'd2;#10 data_in=8'd15;#10 data_in=8'd15;endendinitial #1000 $stop;HDLendmodule2、基于上述異步 FIFO 接口

16、設(shè)計(jì)的分析，分模塊對(duì)電路進(jìn)行建模，HDLI苗述如下：(1) 控制單元module control_unit(inout read,input write,input stk_empty,input stk_full,output read_fr_stk,output write_to_stk);assign write_to_stk=(write && (!stk_full);assign read_fr_stk=(read && (!stk_empty);endmodule(2) 數(shù)據(jù)通道單元Module datapath_unit #(parameter s

17、tack_width=8,stack_depth=16,poiter_width=4) (input clk_write, input clk_read, input rst, input read_fr_stk, input write_to_stk,input poiter_width-1:0write_ptr, input poiter_width-1:0read_ptr, inputstack_width-1:0 data_in, output reg stack_width-1:0 data_out); reg stack_width-1:0 stackstack_depth-1:0

18、;integer i;always (posedge clk_write or posedge rst)beginif(rst)for(i=0;i<=15;i=i+1)begin stacki<=8'd0; end else if (write_to_stk) beginstackwrite_ptr<=data_in;endendalways (posedge clk_read /*or posedge rst*/)beginif (read_fr_stk)begindata_out<=stackread_ptr;endend endmodule(3) 狀態(tài)控制

19、單元 module status_unit #(parameter stack_depth=16,stack_half_depth=8,poiter_width=4)(input clk_write, input clk_read, input rst, input read_fr_stk, input write_to_stk, output reg poiter_width-1:0write_ptr, output reg poiter_width-1:0read_ptr, output stk_full, output stk_almost_full, output stk_half_f

20、ull, output stk_almost_empty, output stk_empty);reg poiter_width:0 write_cnt;reg poiter_width:0 read_cnt;wire poiter_width:0 ptr_gap;assign ptr_gap=write_cnt-read_cnt;assign stk_full=(ptr_gap=stack_depth)?1'b1:1'b0;assign stk_almost_full=(ptr_gap=stack_depth-2)?1'b1:1'b0; assign stk_

21、half_full=(ptr_gap=stack_half_depth)?1'b1:1'b0; assign stk_almost_empty=(ptr_gap=2)?1'b1:1'b0;assign stk_empty=(ptr_gap=0)?1'b1:1'b0;always (posedge clk_write or posedge rst)beginif(rst)beginwrite_cnt<=5'd0;endelse if (write_to_stk) begin write_cnt<=write_cnt+5'

22、d1; write_ptr<=write_cntpoiter_width-1:0; endendalways (posedge clk_read or posedge rst)beginif(rst)beginread_cnt<=5'd0;endelse if (read_fr_stk) begin read_cnt<=read_cnt+5'd1; read_ptr<=read_cntpoiter_width-1:0; endend endmodule(4) 頂層設(shè)計(jì)module top_fifo_asyn #(parameter stack_width

23、=8,poiter_width=4)(input clk_write, input clk_read, input rst, input write, input read, inputstack_width-1:0 data_in, output stk_full, output stk_almost_full, output stk_half_full,output stk_almost_empty,output stk_empty,output stack_width-1:0 data_out);wire read_fr_stk;wire write_to_stk;wire poiter

24、_width-1:0write_ptr;wire poiter_width-1:0read_ptr;control_unit U1(read,write,stk_empty,stk_full,read_fr_stk,write_to_stk); datapath_unitU2(clk_write,clk_read,rst,read_fr_stk,write_to_stk,write_ptr,read_ptr,data_ in,data_out);status_unit U3(clk_write,clk_read,rst,read_fr_stk,write_to_stk,write_ptr,re

25、ad_ptr,stk_f ull,stk_almost_full,stk_half_full,stk_almost_empty,stk_empty);endmodule(5) testbench timescale 1ns/1nsmodule tb_top_fifo_asyn #(parameter stack_width=8);reg clk_write;reg clk_read;reg rst;reg write;reg read;regstack_width-1:0 data_in;wire stack_width-1:0 data_out;wire stk_full,stk_almos

26、t_full,stk_half_full,stk_almost_empty,stk_empty; top_fifo_asynU(clk_write,clk_read,rst,write,read,data_in,stk_full,stk_almost_full, stk_half_full,stk_almost_empty,stk_empty,data_out);initialbegin clk_read=0; clk_write=0; rst=0; write=0; read=0; data_in=0;endalways #17 clk_write=clk_write; always #5

27、clk_read=clk_read; initialbegin#10 rst=1;#10 rst=0;end initialfork#34 write=1;#1020 write=0;#1496 write=1;#580 read=1;#1000 read=0;#1500 read=1;join initialbegin#34 repeat(10) begin#34 data_in=8'd2;#34 data_in=8'd0;#34 data_in=8'd1;#34 data_in=8'd3;#34 data_in=8'd2;#34 data_in=8&

28、#39;d2;#34 data_in=8'd2;#34 data_in=8'd4;#34 data_in=8'd0;#34 data_in=8'd2;#34 data_in=8'd3;#34 data_in=8'd2;#34 data_in=8'hFF;#34 data_in=8'hFF;endend initial #2000 $stop; endmodule四、設(shè)計(jì)仿真1、選擇合適ALTERA勺FPGA芯片，對(duì)上述兩種設(shè)計(jì)進(jìn)行編譯、分析、綜合。然后利用MODELSI進(jìn)行仿真驗(yàn)證。2、同步FIFO實(shí)現(xiàn)的接口設(shè)計(jì)，基于上述TESTBENCH件，MODELSIM仿真驗(yàn)證結(jié)果如圖 3 所示Iffacidc: ft rati