quartus軟件下的modesim仿真方法

1、、Quartus 2中仿真環(huán)境設(shè)置1、設(shè)置仿真軟件 modelsim-altera 路徑：tools->options->general->eda tool options,彈出對話框:0 OptionsOKEanoelApph=HelpModelsim-altera : C:altera11.0modelsim_asewin32aloem（說明：C:altera11.0modelsim_asewin32aloem 為 modelsim 安裝路徑） 點(diǎn)擊：ok2、 Assignments->settings->EDA tools settings->simu

2、lation, 彈出對話框:f Sittings - Delay.LINT.SiECategary:Gene<alUturanes?；豈ug Setting and VolUige Temperature Com制肌ion啟 SettMigsEart Timing Estimate Tncr«men£al Compiln Ptiyacal Syntiieas Optinwz的。fieEDA Tocl beltingsDesign Enby/S 河 the* SimAjIatiDmTinwig AiiaSitS Formal Venficatjon Board-Leve

3、lAnssis & Synthesis Settings VHDL EnputVtfiiog HDL mpaDefault ParatmetprsFitter SettingsTirneQiw或 Tuning Analyzer AssemMerDesign Assint寫ignMT叩 II Logic AnalyzerL啊k Analyzer knrerface附wwrPIdy Power Analyzer SettingsSStJ AnalyzerIII：Tool name: modelsim - altera;Format for output netlist : verilog

4、hdl ;設(shè)置好后，點(diǎn)擊 apply和ok；3.測試平臺設(shè)計(自動生成測試平臺模板文件) 先將Con_Motor.v文件設(shè)置為頂層文件；Processing->start->start test bench template writer,如圖:Tools Window心口叩防蛇通SSi旭Qrl-Shift+CSAil CnirplBbtHi'Clrl-H.M .AnaMe- Crrent File，巡© ? a金也0噎辱 她燈Project碧Cwi-MMiif.v格 srnJzlxrx'nwdDkimi'CDn Mnlur.Mf QFl*5麻&a

5、mp; 口的囹1# 1 F三 。File Edit View Frnipect 冷則inme減5盟 Quartus H - F：Aestl/test_mMor - test_mot國 sntdfllJwlTOdrfeimjiC<jn_MtfLDr.vlScanV 5%n| Anahw & EWwrfllKjnensa產(chǎn) Can_M0cir.v其 utsc.frmf.btirMemo加工通用1寅陽File& Cwnpl蚪m ReportOrltRM PicriterPlav Pow«f 啟同咫即 Tool號 5tMi AnahS 4 即tH*；Ori+KSt&am

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7、SM Analyzer* * * *t is freely editable , tion to help cht userGenet/匚etl on n：Test BeSimulation taoj'timescale ins/ Irmodule Can_HD£cir_i/ constants/ general purpose .reg eachG;/ test vector IngSUMCMpilMi«hStaa VO ssmeni: A/MlytisStan Early Tinw$ Estmte5tafi Check 4 5#re AH Meftst Chan

8、gesStfirtVQM Wffljer5 ton EqKjon Wrier (Pas-rrtnesis)5忸4 E*sgn Wrter (Posr-ttoig)Start T日宜Tmplata' XVnter盤Ml EVA寫ynlh就出Starl EDA Physical SnthDBEClrKShrtt+S頂層文件名.vt,即testbench文件與頂層文件名相同;該例為生成的testbench文件路徑：項(xiàng)目Con_Motor.vt 。(1)向設(shè)計工程添加測試平臺文件 Con_Motor.vt ;(2)打開 Con_Motor.vt 文件后：先用雙斜杠屏蔽掉eachvec語句，即屏

9、蔽掉eachvec語句；(把eachvec注釋掉才能得到一段很長的波 形，不然仿真時間就非常短，如果在它之前有在這個always過程塊里規(guī)定時鐘信號的翻轉(zhuǎn)的話，這個時鐘信號也不會翻轉(zhuǎn)?？傊?，注釋掉它。)添加激勵信號clk和command,修改后的測試平臺文件如下：'timescale 1ns/ 1nsmodule Con_Motor_vlg_tst();/ constants/ general purpose registers reg eachvec;/ test vector input registersreg CLK;reg Command;/ wireswire CP;/ a

10、ssign statements (if any)Con_Motor i1 (/ port map - connection between master ports and signals/registers.CLK(CLK),.CP(CP),.Command(Command) );initialbegin/ code that executes only once/ insert code here -> beginCLK =0;Command =0;#5 Command =1;/ -> end$display("Running testbench");en

11、dalways/ optional sensitivity list/ (event1 or event2 or . eventn)begin/ code executes for every event on sensitivity list/ insert code here -> begin#1 CLK <= CLK;/eachvec;/ -> endendendmodule(1)向仿真工程 添加測試平臺文件:Assignments->settings->simulation->compile test bench , 如圖:uArlus U F;/l

12、白史 1/加%.15卅-削tesLm 承 w凰雷 目您1*電飛電號海 1媯中單擊“test benches.：',如圖:單擊“ new”，如圖:/ New Test Bench SettingsTest bench name：測試平臺名，即.vt的文件名；Top level module in test bench : test bench 中頂層模塊名，即 testbench 中的待測模塊名；注意：Top level module in test bench 必須和testbench 中的待測模塊名一致；Test bench files欄的File name項(xiàng)：測試平臺文件名，和 T

13、est bench name相同，即.vt的文件名，單擊進(jìn)行瀏覽，找到.vt文件, 該.vt文件的瀏覽圖：單擊open打開；單擊ADD添加后，圖:單擊ok后，如圖:單擊“ok”后，如圖:單擊apply,再單擊ok,完成測試平臺向仿真工程的添加。4、仿真:鉗 Quartus U - G：/quartu52/1int_srnn/Oelay_LlNT - DelayUNTFile Edit View Project Assignments Ftdceesi呷i | TcmAs Window Help 中虎。Q 昌 國/配 sc Del Run EDA Smulatian TddIRun EDA Ti

14、mifKi Analy3s Tehol 立 Laundh EDA Simulation Ubrary Compiler Q Laundi 幽即 Space Explorer。TimeQuegt Timing AnalyzerAdvisarsProject Movigator Flies尸 加 lziV_UNT*卷電«G百西的卷B#Chip Planner (Roftfplan and Editor) Design Partition Planner NM 幅 ViewersSignaFTap 口 Logic Analyzer in-ystein Memory Content Edit

15、or Loic Analyzer Interface Edrtor m-Systefn Sources and Probes Edrtor SlgnalPratie Pins.Fr-&gramm&rIT AG Chain Debitter Tran?cehfigr Tglht Eternal 陷eMCuy Tnterfaoe TglkltEDA RTL Simulation>EM Gate Level Simultallcm% fl G Q 像r I 一 tput files from any of a gramming or simulation : ion or in

16、formation are * it ions af the Altera Pri tP Altera. Megacort Func ppiicable license agreec hat your use is for the ices manufactured by Al- zed distributors = Plea： for further dwt百il5.* * * Verilog test bench temp： mments are provided in tails,*京黃宜優(yōu)育曲育育青育育育/*015 14:50:27"mplate for design : D

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18、，育戊育育官育青*育黃黃黃信命甘te_ se11 ings_file s=o f f D sinn/$ imula ti on/made IsimorSr 0 warningsquartus會自動打開 modelsim ,如圖:M HoWSiE ALTEW SlAfiTLA EDfUON 6.6d日白 Edit Witw Compile Simure Add Wm TqoK L/XXI Wndow Help由電戳 |*，i *1 18 p-省51 色Wfi；口 號內(nèi) | .附甲 HE 4| u：|ia±0.Datiaulh“L%wrw“Z”_LHr kfadahtwue 百tri v

19、ua#File Edit ViWi Add Fcrmw Too Is WindowMrj.LNTJ|Mir.UMTE FimpsaWa|t * w| 1M 忖n u Kt 1H什整林雪?田KWW9G. FKkEf!Ntfna!Tw： weip*LC1I3H«1*OrreniHlWH«tM亶RHfcter口中。 &工電iai*5：哈 帝uq哥IL±b r地 A % 里 .%Q " E 2 p?注意：如果已經(jīng)有其他工程的測試平臺文件,則可按照當(dāng)前工程和硬件對其修改,修改后類似添加.v文件的方法，將其直接添加到工程，省去生成測試平臺文件的過程。基于Mo

20、delSim實(shí)現(xiàn)測試平臺仿真1、創(chuàng)建工程打開ModelSim后，選擇:M MddelSim ALTERA SI ARTER EDON 6.&d Custoin Alttra VcrtianFiite | Edit View Compile Simulate Add Project Tools Layout Window HelpNew i3pen.r.S4, : lose Import £xjwd &3昵folderSourcePfDJHICt.ybrary_8J fiegressiiMi.林歌汽.M 舟甯坨鼻 X* *艮圜、匕2忖口加三士燈Sjjye Aa.uRep

21、ori.Qang# Directcry-,- yse Source.Source Direct047.ErrcinirnwtFa5e Setups, font.Ptifit叱浜5風(fēng)rRecent PjcectonesRecent Projects Ck»e Windowquit，Ventag 1/ Venlog 010/03/15 06：32: 31W/®e/l5 05：54;Q3 M/20/11 05rlfl：53 04/2即 U 01t25:3£l單擊Project.后，如圖:Project name下輸入英文的工程名，如 test_Con_Motor ;Pr

22、oject location下，通過browse瀏覽工程路徑，一般選擇測試平臺文件（本例為Con_Motor.vt）所在路徑，如圖:單擊testl后，選擇確定后，如圖:而 Create Project單擊ok,如圖:（注意瀏覽文件時Modelsim ALTERA STARTER FDEON 6一6d - Custom Aftera Version單擊add existing file添加Con_Motor.vt文件后，在工程管理界面下會出現(xiàn)該文件，如圖:選擇文件屬性為all files,否則看不到Con_Motor.vt文件）J M r/occ Sin ALTERA STARTER EDITI

23、ON 6.6d Custom Altera VersionFile Edit View Compile Simulate Add Project Tools Layout Window HelpJ ,安逋立信j M瑜褊 2 i潞* M囂:電M 多皤i福圃|酒次旦畫片小 兇 Project - F: testl test_Coin_Motor_t Namer Statu! Type Orde ModifiedCbn_Motar.vt ? Verilog 010/1S/1510:15:46 AM單擊Con_Motor.vt文件，右鍵選擇 complie再選擇compile selected,如圖:

24、File Edir View Compile Simulate Add Project Tools Layout Window Help 成或I X電磁發(fā)2i . -M能,口 穆圈育妻 注次國周旗Layout1 CQn_MotflRvt Verilog 0 ia/lfl/15 EditExecuteCompileCompile SelectedAdd： to ProjectlRemove from Project Cluse Project UpdateCompile AllCompile Out-of-DateCompile Order.-Compile R&port.Compile

25、 SurnmarY，a+PropwrtiQR-.Project S atti ng $Compile Pnoperti編譯后，問號變對勾，出現(xiàn)successful表明文件無語法錯誤，如圖:CT Project - Fmnt*_Si_MQl:cji 1Name5MujTypeDrdeiModifiedj Ct>n_MQtor.vt Verilog 0 lO/lfiMS 10:15:46 AM鼻UbEq/的i即叩rt TEMQryt Loading prajact teBt_Ceni_McitD-it Comp lie of CDnHotar K vt iras succe ssEul jM

26、白配店im>2、設(shè)置工作組Library管理界面下，work提示unavailable ,表明當(dāng)前工作組不可用；選擇work,單擊右鍵，選擇 edit如圖:M Lv1 odelSim ALTERA STARTER EDHION 6.6d - Custom Altera VerticnlFite Edit View Compile Simulate Add Library Took Layout Window Help國四職必XOX劇典1 九 hardoapyi¥_pde_hip Library+ ft mas+ M m®cii± jj. m已加±

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30、 |更I升班或J彈出界面如圖:browse瀏覽,找到testl,再找到 work ,如圖:選擇確定后，如圖:M Edit Library MappingUbrary Mapping Name| worklibrary PathnaineF:/testl/workBrowse.ok | cancel |選才i ok后，如圖:U M ModelSim ALTERA STARTER EDITION 6.6d - Custom AlteraFile Edit View Compile Simulate Add Library Tool Layout Window Help，不通中總/電型三r 舞群必記

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35、loUbrorytMODEL_TEOH/BVvenlDga & VltatZODDUbrarySJMOOELTEOH/rr/vftalZOW二 JUl workLibmiyF:/lE5tl/wnrk-D Con_Motor_ylgLtaModuleFr/te/simuiation/modelsim/Con.Mo.此 library 1ti Frojsrt表明Con_Motor.vt文件添加到當(dāng)前工作組（上一步的 work提示unavailable消失），注意此時Con_Motor文件被系 統(tǒng)白勺 Con_Motor_vlg_tst 替換；Project管理界面下，單擊Con_Motor

36、.vt測試平臺文件，右鍵add to project,選擇existing file.,準(zhǔn)備添力口 Con_Motor.v源文件文件，如圖:File Ediit View Compile Simulate Add Project Tools Layout Window Help口,50小高一勤媽二3 ! Q*號KJ 啰幽魏國 引小*，£邸ColumnLaout jAilColunma添加Con_Motor.v源文件 文件，編譯后如圖:ModelSim ALTERA STARTER EDITION 6.6dIH_| Con_Mob0nvt Q Con_MotjonvFile Edit

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38、* Loading work-Con_Moto r# Compile of Con_Motor > v wan 3uccieasfill.編譯成功后Con_Motor.v源文件會自動添加到當(dāng)前工作組，如圖:Model Sim ALTERA STARTER EDITION 6；File Edit View Compile Simulate Add Library Tools Layout Window Help 4需南3彳啊塔修叱判器由彳圖兇藥寄到* :圖CotumnLaryDiit AllCoLumns血 LibER Name|t儼冏h二+皿出UMg5MODEk.TEa-v.sittra

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