ARMCoreFamilyApplicationCoresEmbeddedCoresS……

1、ARM Core FamilyApplication CoresEmbedded CoresSecure CoresARM720TARM7EJ-SSecureCore SC100ARM920TARM7TDMISecureCore SC110ARM922TARM7TDMI-SSecurCore SC200ARM926EJ-SARM946E-SSecurCore SC210ARM1020EARM966E-SARM1022ARM968E-SARM1026EJ-SARM996HSARM11 MPCoreARM1026EJ-SARM1136J(F)-SARM1156T2(F)-SARM1176JZ(F)

2、-SARM Cortex-M0ARM Cortex-A8ARM Cortex-M1ARM Cortex-A9ARM Cortex-M3T: ThumbD: On-chip debug supportM: Enhanced multiplierI: Embedded ICE hardwareT2: Thumb-2S: Synthesizable codeE: Enhanced DSP instruction setJ: JAVA support, JazelleZ: Should be TrustZone?F: Floating point unitH: Handshake, clockless

3、 design for synchronous orasynchronous designARM processor core + cache + MMU = ARM CPU coresARM6 ARM7 3-stage pipeline Keep its instructions and data in the same memory system Thumb 16-bit compressed instruction set On-chip Debug support, enabling the processor to halt inresponse to a debug request

4、 Enhanced Multiplier, 64-bit result Embedded ICE hardware, give on-chip breakpoint andwatchpoint supportqARM8 ARM9 ARM10qARM9 5-stage pipeline (130 MHz or 200MHz) Using separate instruction and data memory portsqARM 10 (1998. Oct.) High performance, 300 MHz Multimedia digital consumer applications O

5、ptional vector floating-point unitqARM11 (2002 Q4) 8-stage pipeline Addresses a broad range of applications in the wireless,consumer, networking and automotive segments Support media accelerating extension instructions Can achieve 1GHz Support AXIqSecurCore Family Smart card and secure IC developmen

6、tqCortex Family Provides a large range of solutions optimized aroundspecific market applications across the full performancespectrum ARM Cortex-A Series, applications processors forcomplex OS and user applications. Supports the ARM, Thumb and Thumb-2 instruction sets ARM Cortex-R Series, embedded pr

7、ocessors for real-timesystems. Supports the ARM, Thumb, and Thumb-2 instruction sets ARM Cortex-M Series, deeply embedded processorsoptimized for cost sensitive applications. Supports the Thumb-2 instruction set onlyARM Architecture VersionVersion 1 The first ARM processor, developed at Acorn Comput

8、ers Limited1983-1985 26-bit address, no multiply or coprocessor supportVersion 2 Sold in volume in the Acorn Archimedes and A3000 products 26-bit addressing, including 32-bit result multiply andcoprocessorVersion 2a Coprocessor 15 as the system control coprocessor to managecache Add the atomic load

9、store (SWP) instructionqVersion 3 First ARM processor designed by ARM Limited (1990) ARM6 (macro cell)ARM60 (stand-alone processor)ARM600 (an integrated CPU with on-chip cache, MMU, writebuffer)ARM610 (used in Apple Newton) 32-bit addressing, separate CPSR and SPSRs Add the undefined and abort modes

10、 to allow coprocessoremulation and virtual memory support in supervisor modeqVersion 3M Introduce the signed and unsigned multiply and multiplyaccumulateinstructions that generate the full 64-bit resultVersion 4 Add the signed, unsigned half-word and signed byte load and storeinstructions Reserve so

11、me of SWI space for architecturally defined operation System mode is introducedq Version 4T 16-bit Thumb compressed form of the instruction set is introducedq Version 5T Introduced recently, a superset of version 4T adding the BLX, CLZ andBRK instructionsq Version 5TE Add the signal processing instr

12、uction set extensionqVersion 6 Media processing extensions (SIMD) 2x faster MPEG4 encode/decode 2x faster audio DSP Improved cache architecture Physically addressed caches Reduction in cache flush/refill Reduced overhead in context switches Improved exception and interrupt handling Important for imp

13、roving performance in real-time tasks Unaligned and mixed-endian data support Simpler data sharing, application porting and saves memoryThe Pipeline The pipeline is used to overcome the delay caused by instruction fetching and decoding before execution.q Fetch The instruction is fetched from memory

14、and placed in the instruction pipelineq Decode The instruction is decoded and the datapath control signals prepared for thenext cycleq Execute The register bank is read, an operand shifted, the ALU result generated andwritten back into destination registerq The three stage pipeline has hardware inde

15、pendent stages that execute one instruction while decoding a second and fetching a third.qPC runs 8 bytes ahead of current execution instruction since it holds the address of the fetching instruction but not the current execution instruction.0x4000LDR PC,PC,#4 results PC => 0x400C not 0x4004Proce

16、ssor Modesn The ARM has seven basic operating modes:n User : unprivileged mode under which most tasks runn FIQ : entered when a high priority (fast) interrupt is raisedn IRQ : entered when a low priority (normal) interrupt is raisedn Supervisor : entered on reset and when a Software Interrupt instru

17、ction is executedn Abort : used to handle memory access violationsn Undef : used to handle undefined instructionsn System : privileged mode using the same registers as user modeRegistersn ARM has 37 registers all of which are 32-bits long.o 1 dedicated program countero 1 dedicated current program st

18、atus registero 5 dedicated saved program status registerso 30 general purpose registersProgram Status Registers (CPSR & SPSR)2731N Z C V Q2867I F T mode1623 815 54024fsxc U n d e f i n e dJn Condition code flagsn N = Negative result from ALU n Z = Zero result from ALUn C = ALU operation Carried

19、outn V = ALU operation oVerflowedn Sticky Overflow flag - Q flagn Architecture 5TE/J onlyn Indicates if saturation has occurredn J bitn Architecture 5TEJ onlyn J = 1: Processor in Jazelle staten Interrupt Disable bits.n I = 1: Disables the IRQ.n F = 1: Disables the FIQ.n T Bitn Architecture xT onlyn T = 0: Processor in ARM s