用vhdl語言設(shè)計(jì)計(jì)數(shù)器

1、76進(jìn)制計(jì)數(shù)器LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU_76 IS PORT (CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END CDU_76; ARCHITECTURE AA OF CDU_76 IS SIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF (CLK'EVENT AND CLK

2、='1') THEN IF(COUT2=7 AND COUT1=5) THEN COUT2<="0000"COUT1<="0000" ELSE IF (COUT1=9) THEN COUT2<=COUT2+1;COUT1<="0000" ELSE COUT2<=COUT2;COUT1<=COUT1+1; END IF; END IF; END IF; END PROCESS; Q<=COUT2&COUT1; END AA;24進(jìn)制計(jì)數(shù)器LIBRARY IEEE;USE

3、IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CDU_24 ISPORT (CLK:IN STD_LOGIC;Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CDU_24;ARCHITECTURE AA OF CDU_24 ISSIGNAL COUT2,COUT1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF (CLK'EVENT AND CLK='1') THEN IF(COUT2=2 AND CO

4、UT1=3) THEN COUT2<="0000"COUT1<="0000" ELSE IF (COUT1=9) THEN COUT2<=COUT2+1;COUT1<="0000" ELSE COUT2<=COUT2;COUT1<=COUT1+1; END IF; END IF;END IF;END PROCESS;Q<=COUT2&COUT1;END AA;用VHDL 設(shè)計(jì)一個(gè)帶高電平使能信號(hào)、低電平清零信號(hào)、低電平置數(shù)信號(hào)的十進(jìn)制計(jì)數(shù)器LIBRARY IEEE;USE IEEE.S

5、TD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(CLK,SET,CLR,EN:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC);END CNT10;ARCHITECTURE behav OF CNT10 ISBEGINPROCESS(CLK,SET,CLR,EN)VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR='0' THEN CQI:=(OTHERS=>'0'); ELSIF CLK'EVENT AND CLK='1' THENIF SET='0' THEN CQI:=(OTHERS=>'1'); ELSIF EN='1' THEN IF CQI<9 THEN CQI:=CQI+1; ELSE CQI:=(OTHERS=>'0'); END IF; END IF; END IF; IF CQI=9 TH