第五講單周期處理器kong zhi xin hao de

1、信號的集成·慕課計算機(jī)組成制作人：林本節(jié)主題現(xiàn)有指令所需的信號Instruction<31:0>nPC_selclkrd515rt50RegDstRegWrrs5rt5MemtoRegALUCtrMemWrzerorsrtrdimm16busA32=busW320busB32032AdrWrEnDataData In3211imm1632Memory1632clkExtOpALUSrc<15: 0 ><15:11><20:16><25:21> Extender ALURwRa RbRegFile32-bit×32c

2、lkIFU處理器的設(shè)計步驟 分析指令系統(tǒng)，得出對數(shù)據(jù)通路的需求 為數(shù)據(jù)通路選擇合適的組件 連接組件建立數(shù)據(jù)通路 分析每條指令的實現(xiàn)，以確定信號邏輯 集成信號，形成完整的邏輯與數(shù)據(jù)通路Instruction Word32opcodefuncrsrtrdimm16邏輯nPC selRegWrRegDstExtOpALUSrcALUctrMemWrMemtoReg<15: 0 ><15:11><20:16><25:21> < 5:0 > <31:26>數(shù) 據(jù) 通 路AddressInstruction Memory信號的匯總（以

3、add指令為例）¬¬add:RrdRrs+Rrt;PCPC+4Instruction<31:0>nPC sel=“+4”clkIFUrd515rt50RegDst=1RegWr=1rs5rt5MemtoReg=0ALUCtr=“ADD”MemWr=0rsrtrdbusA32zero=busW320busB32032AdrWrEnDataData In3211imm1632Memory1632clkExtOp=xALUSrc=0<15:11><20:16><25:21> Extender ALURwRa RbRegFile32-

4、bit×32clk信號的邏輯表達(dá)式funcopcode(op)100000100010/000000000000001101100011101011000100addsuborilwswbeqRegDst1100xxALUSrc001110MemtoReg0001xxRegWr111100MemWr000010nPC_sel000001ExtOpxx011xALUctr<1:0>00(ADD)01(SUB)10(OR)00(ADD)00(ADD)01(SUB)信號的邏輯表達(dá)式RegDst=add+subaddsub=rtype·=rtype·func5

5、·func4·func3·func2·func1·func0func5·func4·func3·func2·func1·func0rtype=op5·op4·op3·op2·op1·op0add,ori,sublw,Rsw,beqIopcodersrtimmediateopcodersrtrdshamtfunctfuncopcode(op)100000100010/000000000000001101100011101011000100addsu

6、borilwswbeqRegDst1100xx器的邏輯表達(dá)式RegDst ALUSrc MemtoReg RegWr MemWr nPC_sel ExtOp ALUctr0 ALUctr1=add ori lw add sw beq+sublw + sw+sub + ori+ lwlw + sw sub + beq oradd sub rtype ori lwsw beq=rtype·func5·func4·func3·func2·func1·func0 rtype·func5·func4·func3&#

7、183;func2· func1·func0op5·op4·op3·op2·op1·op0,op5·op4· op3· op2·op1· op5·op4·op3·op2· op1· op5·op4· op3·op2· op1·op0 op0 op0op5·op4·op3· op2·op1·op0器的實現(xiàn)示意圖opcode6func6add sub ori lw邏swbeqrtypeRegDst ALUSrc MemtoReg RegWr MemWr nPC_sel ExtOp ALUctr0ALUctr1由或門組成輯的邏輯