以延遲鎖定回路為基礎(chǔ)的全數(shù)位快速鎖定時(shí)脈產(chǎn)生器之設(shè)計(jì)與實(shí)作

1、National Taiwan UniversityDepartment of Electrical Engineering& Graduate Institute of Electronics EngineeringDate : 2006.06.24以延遲鎖定迴路為基礎(chǔ)的全數(shù)位快速鎖定時(shí)脈產(chǎn)生器之設(shè)計(jì)與實(shí)作 Design and Implementation of All-DigitalFast-Locked DLL-Based Clock GeneratorsAdvisor: Shen-Iuan LiuStudent: Chuan_kang LiangElectronic Circuits

2、 Lab.Chuan_kang Liang 2Motivationsl For a clock generator, why DLL?p Unconditional stability: first order systemp No jitter accumulation from the delay linel Why all digital?p Robust and insensitive to PVT variationp Easily to port to advanced processp Fast lock SAR algorithm l The limitations of th

3、e DLLp False lock and harmonic lockp Trade-offs between the operating frequency and operation rangep No frequency synthesisElectronic Circuits Lab.Chuan_kang Liang 3An Ultra Wide-Range Delay-Locked-Loop with Cyclic Techniquel Methodsp New lock algorithmp New duty-cycle correction conceptp Modified S

4、AR algorithm to achieve fast locked and closed loop tracking abilityl Featuresp All digital DLLp Wide range 1520MHz p Fast locked 16 input clockp DCC with single referencep Closed loop after lockedp High extension enlarge range with the same lock time p Small area 0.2mm x0.3mm active areap Low power

5、 smaller than 15mw500MHzElectronic Circuits Lab.Chuan_kang Liang 4An All-Digital Fast-Locked DLL-Based Frequency Synthesizerl Methodsp New selection concept and PFD to eliminate the initial constraint.p Modified SAR algorithm to achieve fast lock and closed loop tracking ability.l Featuresp The first one all-digital DLL-based frequency synthesizer p Multiplication ratio is programmablep Closed loop - deal with environment variationp