EDA技術(shù)習(xí)題解答5

1、EDA技術(shù)習(xí)題5習(xí) 題5-1歸納利用Quartus II進(jìn)彳T VHDL文本輸入設(shè)計(jì)的流程：從文件輸入一直到SignalTap II測(cè)試。P95P115答：1建立工作庫(kù)文件夾和編輯設(shè)計(jì)文件；2創(chuàng)建工程；3編譯前設(shè)置；4全程編譯；5 時(shí)序仿真；6引腳鎖定；7配置文件下載；8打開SignalTap II編輯窗口； 9 調(diào) 入SignalTap II的待測(cè)信號(hào)；10 SignalTap II參數(shù)設(shè)置；11 SignalTap II參數(shù)設(shè)置文件 存盤；12帶有SignalTap II測(cè)試信息的編譯下載；13啟動(dòng)SignalTap II進(jìn)行采樣與分析； 14 SignalTap II的其他設(shè)置和控制方法

2、。5-2由圖5-40和圖5-41 ,詳細(xì)說明工程設(shè)計(jì)CNT10的硬件工作情況。P114P115答：圖5-40給出工程設(shè)計(jì) CNT10的十進(jìn)制計(jì)數(shù)工作情況；當(dāng)計(jì)數(shù) CQ或CQI到9時(shí), 計(jì)數(shù)進(jìn)位COUT輸出正脈沖。圖5-41給出工程設(shè)計(jì) CNT10的十進(jìn)制計(jì)數(shù)和內(nèi)部計(jì)數(shù)節(jié)點(diǎn) CQI計(jì)數(shù)線性遞增的信號(hào)波形的工作情況。5-3如何為設(shè)計(jì)中的 SignalTap II加入獨(dú)立采樣時(shí)鐘？式給出完整的程序和對(duì)它的實(shí)測(cè)結(jié) 果。P115答：為SignalTap II提供獨(dú)立時(shí)鐘的方法是在頂層文件的實(shí)體中增加一個(gè)時(shí)鐘輸入端口， 如語句：LOGC_CLK:INSTD_LOGIC;在此實(shí)體中不必對(duì)其功能和連接具體定義

3、，而在SignalTap II的參數(shù)設(shè)置中則可以選擇LOGC_CLK為采樣時(shí)鐘。5-4參考QuartusII的Help,詳細(xì)說明 Assignments菜單中Settings對(duì)話框的功能。(1)說明其中的Timing Requirements&Qptions的功能、他用方法和檢測(cè)途經(jīng)。Specifying Timing Requirements and Options(Classic Timing Analyzer)You can specify timing requirements for Classic timing analysis that help you achieve the

4、desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins.When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to mee

5、t your timing goals.You can use the Timing wizard or the Timing Analysis Settings囹 command to easilyspecify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes in

6、cluded in a wildcard or assignment group assignment.To specify project-wide timing requirements: A On the Assignments menu, click Settings .In the Category list, select Timing Analysis Settings.To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values under Delay requireme

7、nts .To specify project-wide minimum delay requirements, specify options under Minimum delay requirements.5.6.In the Default required fmaxbox, type the value of the requiredfMAx and select aUnder Clock Settings , select Default required fmaxtime unit from the list.7.If you want to specify options fo

8、r cutting or reporting certain types of timing pathsfollow these steps:globally, enabling recovery/removal analysis, enabling clock latency, and reportingunconstrained timing paths,8.Click OK.To specify clock settings:1.On the Assignments menu, clickSettings2.In the Category list, selectTiming Analy

9、sis Settings3.Under Clock Settings , clickIndividual Clocks4.Click New .5.In the New Clock Settingsdialog box, type a name for the new clock settings in theClock settings namebox.6.the Applies to nodebox, or click Browse. to select a node name using theNodeTo assign the clock settings to a clock sig

10、nal in the design, type a clock node name inFinderIf you want to specify timing requirements for an absolute clock,follow these steps:If you have already specified timing requirements for an absolute clock, and you want to specify timing requirements for a derived clock,follow these steps:In the New

11、 Clock Settings dialog box, click OK .In the Individual Clocks dialog box, click OK.In the Settings dialog box, click OK .To specify individual timing requirements:dSHOn the Assignments menu, click Assignment Editor .In the Category bar, select Timing to indicate the category of assignment you wish

12、to make.In the spreadsheet, select the To cell and perform one of the following steps:Type a node name and/or wildcard that identifies the destination node(s) you want to assign.Double-click the To cell and click Node Finder to use the Node Finder to enter a node name.Double-click the To cell, click

13、 the arrow that appears on the right side of the cell, and click Select Assignment Groupto enter an existing assignmentgroup name.To specify an assignment source, repeat step 3 to specify the source name in theFrom cell.Assignment Namecell and select the timingIn the spreadsheet, double-click the as

14、signment you wish to make.For assignments that require a value, double-click theValue cell and type or selectthe appropriate assignment value.守 To specify timing analysis reporting restrictions: 再回On the Assignments menu, click Settings .In the Category list, double-click Timing Analysis Settings.Cl

15、ick Timing Analyzer Reporting.To specify the range of timing analysis information reported, specify one or more options in the Timing Analyzer Reportingpage.Click OK.(2)說明其中的Compilation Process的功能和使用方法。Compilation Process Settings Page (Settings DialogBox)Allows you to direct the Compiler to use sma

16、rt compilation, save synthesis results for the current designs top-level entity, disable theOpenCorePlus hardware evaluation feature , or export version-compatible database files . You can also control the amount of disk space used for compilation.Use Smart compilation: EHEEIPreserve fewer node name

17、s to save disk space:EEE3Run Assembler during compilation:EEE!Save a node-level netlist of the entire design into a persistent source file:Export version-compatible database:E0G3Display entity name for node name:CHE3Disable OpenCore Plus hardware evaluation feature:(3)說明 Analysis&Synthesis Setting的功

18、能和使用方法，以及其中的Synthesis NetlistOptimization的功能和使用方法。Analysis & Synthesis Settings Page (Settings DialogBox)Allows you to specify options for logic synthesis.Create debugging nodes for IP cores:C3CTIMore Settings:I d I Other options:m 0Message Level:子Advanced:Synthesis Netlist Optimizations Page (Setti

19、ngs DialogBox)Specifies the following options for optimizing netlists during synthesis:Perform WYSIWYG primitive resynthesis:A Perform gate-level register retiming: A 0Allow register retiming to trade off Tsu/Tco with Fmax:(4)說明FitterSettings中的DesignAssistant和Simulator功能，舉例說明它們的使用方法。Design Assistant

20、 Page (Settings Dialog Box)Allows you to specify which rules you want the Design Assistant to apply whenanalyzing and generating messages for a design, and whether you want the Design Assistant to automatically analyze the design during a full compilation.Run Design Assistant during compilation: m 0

21、Design Assistant configuration rule names:。停Advanced: A 0Simulator Settings PageAllows you to specify settings that control simulation processing, such as the type of simulation that should be performed, the time period covered by the simulation, the source of vector stimuli, and other options. Simu

22、lation also allows you to check setup and hold times, detect glitches, and check simulation coverage. You can also provide vector stimuli in aVector Waveform File ( .vwf ), a Compressed Vector Waveform File ( .cvwf ), or a text-based Vector File ( .vec ). You can use Tcl commands and scripts to cont

23、rol simulation and to provide vector stimuli.Simulation Mode: 1Simulation Input: CHEO匿!Automatically add pins to simulation output waveforms: Check outputs: E3EEIWaveform Comparison Settings: 淳 8Setup and hold time violation detection:Glitch detection:Simulation coverage reporting:Report Settings:Ov

24、erwrite simulation input file with simulation results:Disable setup and hold time violation detection for input registers of bi-directional pins: More Settings:不盤5-5概述Assignments菜單中 Assignment Editor的功能，舉例說明。About the Assignment EditorUser Interface and Functionality: Customizing the User Interface:

25、Pin Information:LogicLock Assignments:Assignment Validation and Output:Integration with the Pin Planner:5-6用74148 (8-3線八進(jìn)位優(yōu)先編碼器)和與非門實(shí)現(xiàn) 8421BCD優(yōu)先編碼器，用 3(5)片74139 (2線-4線譯碼器)組成一個(gè) 5-24(4-16)線譯碼器。DOD1A374148:El 0 1 2 3 4 5 6 7 GS AO A1 A2 EO HXXXXXXXXHHHHHLHHHHHHHHHHHHLLXXXXXXX LLLLLHLXXXXXX LHLHLLHL XXX

26、XX LHH L XXXX L H H H L XXXLHHHH L XXLHHHHH L XLHHHHHH L LHHHHHHHLLHLHLHHLHLLLHHLHLHHLLHHHLHHHHU6.A毀AB7JLS139U6BELS，39U7.A現(xiàn) 5139U7B5-7用74283（4位二進(jìn)制全加器）加法器和邏輯門設(shè)計(jì)實(shí)現(xiàn)一位8421BCD碼加法器電路，輸入輸出均是BCD碼，CI為低位的進(jìn)位信號(hào)，CO為高位的進(jìn)位信號(hào)，輸入為兩個(gè)1位十進(jìn)制數(shù)A ,輸出用S表示。1,5-8設(shè)計(jì)一個(gè)7人表決電路(用4位二進(jìn)制全加器)，參加表決者 7人，同意為意為0,同意者過半則表決通過，綠指示燈亮；表決不通過則紅指示燈亮。X0U117432Y0U12 5-9設(shè)計(jì)一個(gè)周期性產(chǎn)生二進(jìn)制序列01001011001的序列發(fā)生器，用移位寄存器或用同步時(shí)序電路實(shí)現(xiàn)，并用時(shí)序仿真器驗(yàn)證其功能。5-10用D觸發(fā)器構(gòu)成按