案例教案數(shù)電

1、1Digital Logic Design and ApplicationJin YanhuaLecture #6CMOS Dynamic Electrical BehaviorOther CMOS Input and Output StructuresUESTC, Spring 2012Jin. UESTC2答疑安排答疑地點(diǎn)：A教2樓教師休息室 電梯/(A202)旁邊答疑時(shí)間：周二中午 1：00-2：00 周二7、8節(jié) 周四3、4節(jié) 周五3、4節(jié) Jin. UESTC3Last Time3.5 CMOS Steady-State Electrical BehaviorLogic Levels

2、 and Noise Margins30%VCC 0.1V HIGHABNOMALLOWVOLmaxVILmaxVIHminVOHminHigh-state DC noise margin Low-state DC noise margin VCC0.1V GND+0.1V 30%VCC 70%VCC Jin. UESTC4Last TimeCircuit Behavior with Resistive LoadsThe load is specified in terms of current.例：P177 3.27 The load make the output voltage dete

3、riorate.Ensure the sourcing and sinking current within specifications.VCC = + 5.0VRThevVThev +Jin. UESTC5Last TimeCircuit Behavior with Nonideal InputsiDVIN12VDDVOUTVIN5.01.53.55.0電壓傳輸特性 電流傳輸特性 The output voltage away from the power-supply rail.Output current , Power ConsumptionCurrent Spikes 3.6.4J

4、in. UESTC6Last TimeFanoutThe sum of the IIL(IIH) values of the driven inputs may not exceed IOLmax (IOHmax) of the driving outputNeed to do Thevenin-equivalent calculation for non-gate loads (LEDs, termination resistors, etc.)Effects of LoadingUnused InputsNever be left unconnectedJin. UESTC73.6 CMO

5、S Dynamic Electrical BehaviorBoth the speed and the power consumption of a CMOS device depend to a large extent on dynamic characteristics of the device and its load. Speed depends on two characteristics:Transition Time (轉(zhuǎn)換時(shí)間)Propagation Delay (傳播延遲) time that output takes to change states time from

6、 input changing to output changingJin. UESTC83.6.1 Transition TimeDepend on two factors:“On” resistance of transistorStray capacitance (寄生電容)VCC = + 5.0VRLRpRnVL+CLIn real digital circuit, the transition time approximately equals the RC time constant.Rise time trFall time tf Jin. UESTC93.6.1 Transit

7、ion TimetrtftrtfHIGHLOWVIHminVILmaxJin. UESTC103.6.2 Propagation DelayVINVOUT time from input changing to output changingJin. UESTC113.6.3 Power ConsumptionPT : the partial short-circuiting of the CMOS output structurePL : the capacitive load on the outputStatic/Quiescent Power Dissipation Dynamic P

8、ower DissipationVDD = +5.0VVOUTVINTpTnCLJin. UESTC123.7 Other CMOS Input and Output Structures1. Transmission GatesWhen EN=0, EN_L=1, the transistors are “off”, A and B are disconnected.When EN=1, EN_L=0, the transistors are “on”, A and B are connected with a low-impedance.The propagation delay is v

9、ery short.ENEN_LABBidirectional device雙向器件Jin. UESTC132. Schmitt-Trigger InputsVOUTVIN5.02.12.95.0I-O transfer characteristic VT+VT-inputswitching thresholdVT+VT-Use feedback internally shift the switching threshold.采用內(nèi)部反饋，邊沿更陡Hysteresis(滯后): the difference between the two thresholds.Logic Symbol: J

10、in. UESTC14Applications of Schmitt-Trigger脈沖鑒幅 波形變換 脈沖整形 Jin. UESTC153. Three-State OutputsVCC ZENAIf EN=0, C=1, Tp=“off” B=1, D=0, Tn=“off” Z = Hi-impedance state or floating stateIf EN=1 C=A , B=0 , D=A Z=A ( 0 or 1 )BCDTpTnAENOUTLogic SymbolJin. UESTC16輸出電平？造成邏輯混亂很大的負(fù)載電流同時(shí)流過輸出級(jí)可使門電路損壞4. Open-Drai

11、n OutputsVCCAZactive pull-up有源上拉VCCB低高有源上拉的CMOS器件其輸出端不能直接相聯(lián)1001M1001MJin. UESTC174. Open-Drain OutputsABZVCCVCCR pull-up resistanceABZLogic SymbolAs small as possible, to minimize the rise time. Cannot be arbitrarily small, it is determined by IOLmaxpassive pull-up無源上拉Applications: driving multisour

12、ce buses; driving LEDs; performing wired logic. Jin. UESTC18Driving LEDsVOLmaxILED = 10 mAJin. UESTC19Multi-source BusesJin. UESTC20ABZVCCVCCRCDVCCZ = Z1 Z2 = (AB) (CD) = (AB + CD)Wired Logic of Open-Drain OutputsZ1Z2Wired AND (線與) 第4章 反演定理 Jin. UESTC213.8 CMOS Logic FamiliesElectrical Characteristi

13、cs (P.144-147 Table3-5/6/7)Symmetric output drive: output can sink or source equal amounts of current.Jin. UESTC223.9 Low-Voltage CMOS Logic and InterfacingP.152 Figure 3-62P.155 3.9.4 SummaryJin. UESTC23TTL Logic Families TTL Logic Levels and Noise MarginsTTL fanoutAsymmetric output drive A TTL Dat

14、a Sheet P167 Table3-10IILmax=0.4 mA IIHmax=20 uAIOLmax=8 mA IOHmax=400 uAJin. UESTC24CMOS/TTL InterfacingNeed to consider: ：Noise Margin, Fan-out, Capacitance LoadsabnormalVOLmax0.5VOHmin2.7VIHmin2.0VOLmax0.8TTLabnormalVOLmax0.33VOLmax0.8VIHmin2.0VOHmin3.84CMOSJin. UESTC2574HCT driving 74LS H-state:

15、 |VOHmin VIHmin| = 1.84V L-state: |VOLmin VILmin| = 0.47VABNORMALVOLmax0.33VOLmax0.8VIHmin2.0VOHmin3.8474HCTABNORMALVOLmax0.5VOHmin2.7VIHmin2.0VOLmax0.874LS74LS driving 74HCT High: 2.7 2.0 = 0.7V Low: | 0.5 0.8 | = 0.3V1. DC Noise MarginJin. UESTC2674HCT driving 74LS Low-state:2. Fanout High-state:

16、“excess” driving capability is available in High-stateCMOS: 74HCTIOH = 4 mAIOL = 4 mAIIH = 1 AIIL = 1 ATTL: 74LSIOH = 400 AIOL = 8 mAIIH = 20 AIIL = 0.4 mA總扇出Jin. UESTC272. FanoutCMOS: 74HCTIOH = 4 mAIOL = 4 mAIIH = 1 AIIL = 1 ATTL: 74LSIOH = 400 AIOL = 8 mAIIH = 20 AIIL = 0.4 mA思考：74LS(TTL)驅(qū)動(dòng)74HCT(

17、CMOS)的情況？為什么說用TTL驅(qū)動(dòng)TTL兼容的CMOS輸入端幾乎不用考慮直流扇出的限制？P96表3-6P97表3-7P115表3-11Jin. UESTC28Logic Families3.8 CMOS FamiliesHC, HCTHigh-speed CMOSTTL compatibleVHC, VHCT (very)AHC, AHCT (advanced)FCT, FCT-T3.10.6 TTL FamiliesH (high-speed)S (Schottky)L, LS (low-power)A, AS, ALS (advanced) F (fast)7454Part Numbe

18、r: FAM nn function Jin. UESTC29Chapter 3 SummaryPositive Logic and Negative LogicBasic Logic FunctionAND, OR, NOTDescription Method: Truth Table, Logic Equation, Logic SymbolCMOS Logic FamilyMOS transistorsBasic CMOS inverter circuitCMOS NAND, NOR, AOI and noninverting GatesJin. UESTC30Chapter 3 Sum

19、marySteady-State Electrical BehaviorLogic levels and noise marginsResistive loads, Nonideal inputs, Effects of loading fanout, and unused InputsDynamic Electrical BehaviorSpeed: transition time and propagation delay static and dynamic power consumptionCurrent spikesJin. UESTC31Chapter 3 SummaryOther CMOS Input and Output StructuresTransmission GatesSchmitt-Trigger InputsThree-State OutputsOpen-Drain OutputsBipolar Logic: TTLCMOS/TTL InterfacingJin. UESTC32Chapter 3 Task （P175180）3.1 (