AHDL語法入門Altera公司提供

1、AHDLTraining ClassDanny MokAltera HK FAE(dmo)1What is AHDLAltera Hardware Description Languagedevelop by Alteraintegrate into the Altera software Max+Plus IIdescription the hardware in language instead of graphiceasy to modifyeasy to maintanevery good forcomplex combinational logic BCD to 7 Segment

2、converteraddress decodingstate machinemore than you want.2continue.As easy as Graphic EntryAs powerful as HDL (Hardware Description Language) VHDL, Verilog HDL etc.3How to use the ADHLuse any text editor to create the fileAltera Software Max+Plus II provide text editorClick the buttonType in your AH

3、DL design file 4continue.Create your AHDL file5continue.save your ADHL name.TDFMust bethe same6continue.Clickon thisicon7Error Location during CompilationEasy to locate the errorClick theerror message Click the Locate buttonError location8AHDL TemplateI forgot .If-then-elsecase-end caseloop-end loop

4、?Modify the code9General AHDL FormatSUBDESIGN decode1( input_pin_name : INPUT; input_bus_name15.0 : INPUT; output_pin_name : OUTPUT; output_bus_name : OUTPUT;)BEGINouptut_pin_name = input_pin_name;output_bus_name = input_bus_name;END;Key WordDefien I/O portLogic AHDL format10Your First AHDL design -

5、 Address DecoderChip_enable = a0 & a1 & a2 & !a3SUBDESIGN decode1( a3.0 : input; chip_enable : output;)beginchip_enable = (a3.0 = H7);end;11Why I use AHDL instead of GraphicEasy to Modify Document during the codingI want to decode H”A” not H”7”SUBDESIGN decode1( a3.0 : input; chip_enable : output;)b

6、eginchip_enable = (a3.0 = HA);end;Self Explain the FunctionOnly thing to changeNeed more effort to modifyChip_enable = !a0 & a1 & !a2 & a312MoreSUBDESIGN decode1( a3.0 : input; chip_enable : output;)beginchip_enable = (a3.0 = B1x0 x);end;Some bit can be ignore for comparsion13Something you need to k

7、nowAddition : +Subtraction : -Numeric Equality : =Not equal to : !=Greater than : Greater than or equal to : =Less than : Less than or equal to : highest_level = B”1000”;when 2 = highest_level = B”0100”;when 1 = highest_level = B”0010”;when others = highest_level = B”0001”;end case;end;What is the u

8、sage of this statement2526For LoopCONSTANT num_of_bit = 8;SUBDESIGN numbit( anum_of_bit.0 : input; bnum_of_bit.0 : output;)beginb8 = a0;b7 = a1;b6 = a2;b5 = a3;b4 = a4;b3 = a5;b2 = a6;b1 = a7;b0 = a8;end;CONSTANT num_of_bit = 8;SUBDESIGN numbit( anum_of_bit.0 : input; bnum_of_bit.0 : output;)beginfo

9、r i in 0 to num_of_bit generatebnum_of_bit - i = ai;end generate;end;easier with same functionCONSTANT num_of_bit = 8;SUBDESIGN numbit(anum_of_bit.0 : input; bnum_of_bit.0 : otuput;)beginbnum_of_bit.0 = a0.num_of_bit;end;27AHDL with GraphicUse the to create Symbol for the AHDL designThe symbol can b

10、e used for graphic entry28Register LogicMethod 1Method 2SUBDESIGN flip_flop( d, clk : input; q : output;)beginq = dff(d,clk, ,);end;SUBDESIGN flip_flop( d, clk : input; q : output;)variable temp : dff;begintemp.d = d;temp.clk = clk;q = temp.q;end;I want a D-Flipflop29More Detail30More on RegisterHow

11、 to do the Bus with RegisterHow to do the other type of RegisterDFFE (D-FF with enable)TFF/TFFEJKFF/JKFFESRFF/SRFFE31Register BusesSUBDESIGN bus_reg( clk, d7.0 : input; q7.0 : output;)variable ff7.0 : dff;beginff.clk = clk;ff.d = d;q = ff.q;end;ff0.clk = clk;ff1.clk = clk;ff2.clk = clk;ff3.clk = clk

12、;ff4.clk = clk;ff5.clk = clk;ff6.clk = clk;ff7.clk = clk;ff0.d = d0;ff1.d = d1;ff2.d = d2;ff3.d = d3;ff4.d = d4;ff5.d = d5;ff6.d = d6;ff7.d = d7;q0 = ff0.q;q1 = ff1.q;q2 = ff2.q;q3 = ff3.q;q4 = ff4.q;q5 = ff5.q;q6 = ff6.q;q7 = ff7.q;32D-Flip-Flop with Enable/Preset/ClearSUBDESIGN flip_flop_enable( c

13、lock, data, enable, preset, clear : input; qout : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDESIGN flip_flop_enable( clock, data, enable, preset, clear : input; qout : output;)variable te

14、mp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDESIGN flip_flop_enable( clock, data, enable, preset, clear : input; qout : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.

15、prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDESIGN flip_flop_enable( clock, data, enable, preset, clear : input; qout : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDE

16、SIGN flip_flop_enable( clock, data, enable, preset, clear : input; qout : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDESIGN flip_flop_enable( clock, data, enable, preset, clear : input; qo

17、ut : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQSUBDESIGN flip_flop_enable( clock, data, enable, preset, clear : input; qout : output;)variable temp : dffe;begintemp.d = data;temp.clk = clock

18、;temp.clrn = clear;temp.prn = preset;temp.ena = enable;qout = temp.q;end;DCLKCLRNPRNENAQ33Other Type of Flip-Flop34How to use Help MenuQ : I dont know how to use Altera DFF/JKFFE, what can I do ?A : Altera Help Menu is a good place to find informationQ : How do I use the Help Menu ?A : It is easy an

19、d FunDFFE35How to use Help Menu36Tri-state BufferMethod 1Method 2SUBDESIGN tri_state(a, enable : input; b : output;)beginb = tri(a, enable);end;SUBDESIGN tri_state( a, enable : input; b : output;)variable temp : tri;begintemp.in = a;temp.oe = enable;b = temp.out;end;37More Detail38OPNDRN - Open Drai

20、n BufferMethod 1Method 2SUBDESIGN opn_drn(enable : input; b : output;)beginb = opndrn(enable);end;SUBDESIGN tri_state( enable : input; b : output;)variable temp : opndrn;begintemp.in= enable;b = temp.out;end;39More Detail40Using AHDL as EASY as SchematicbutUsing AHDL is more POWERFUL 41ExerciseAHDLS

21、UBDESIGN tri_io( clk, enable : input; io : bidir;)variabletemp1 : dff;temp2 : tri;begintemp1.d = io;temp1.clk = clk;temp2.in = temp1.q;temp2.oe = enable;io = temp2.out;end;inputbidirclk, enable : input;io : bidir;42Design 8 bits Counter is EasySUBDESIGN 8bits(clk : input; q7.0 : output;)variable tem

22、p7.0 : dff;begintemp.clk = clk;temp.d = temp.q +1 ;q = temp.q;end; 43State MachineSUBDESIGN simple( clk, reset, jump : input; q : output;)variable ss : MACHINE WITH STATES (S0,S1);beginss.clk = clk;ss.reset = reset;case ss is when s0 = q = gnd; if (jump) then ss = s1; end if; when s1 = q = vcc; if (

23、jump) then ss = s0; end if;end case;end;State Machine DiagramNote : All State Machine Variable mustbe associated with a CLOCKS0S1jump=1jump=1q = 0q = 1jump=0jump=044if (jump) thenss = s1;end if;if (jump) thenss = s0;end if;45More about State MachineSUBDESIGN stepper( reset, ccw, cw, clk : input; pha

24、se3.0 : output;)variable ss : MACHINE OF BITS (temp3.0) WITH STATES ( s0 = B”0001”, s1 = B”0010”, s2 = B”0100”, s3 = B”1000”);beginss.clk = clk;if (reset) thenss = s2;end if;phase = temp; TABLE ss, ccw, cw = ss; s0, 1, x = s3; s0, x, 1 = s1; s1, 1, x = s0; s1, x, 1 = s2; s2, 1, x = s1; s2, x, 1 = s3

25、; s3, 1, x = s2; s3, x, 1 = s0;END TABLE;end;Note : No need to declare what is TEMPIt is automatic declare as DFF46User can control the State Bit47ExerciseSUBDESIGN stepper( reset, ccw, cw, clk : input; phase3.0 : output;)variable ss : MACHINE OF BITS (temp3.0) WITH STATES ( s0 = B”0001”, s1 = B”001

26、0”, s2 = B”0100”, s3 = B”1000”);beginss.clk = clk;if (reset) thenss = s2;end if;phase = temp; TABLE ss, ccw, cw = ss; s0, 1, x = s3; s0, x, 1 = s1; s1, 1, x = s0; s1, x, 1 = s2; s2, 1, x = s1; s2, x, 1 = s3; s3, 1, x = s2; s3, x, 1 = s0;END TABLE;end;Can you Modify this Truth Table to CASE statement

27、48State Machine without Recover StateSUBDESIGN recover( clk, go : input; ok : output;)variable sequence : MACHINE OF BITS (q2.0) with STATES ( idle, one, two, three, four, illegal1, illegal2, illegal3);beginsequence.clk = clk;case sequence iswhen idle = if (go) then sequence = one; end if;when one = sequence = t