外文翻譯-數(shù)字頻率合成器及外文翻譯-基于移相器的次同步振蕩阻尼

附錄2：外文原文，譯文ModulatingDirectDigitalSynthesizerInthepursuitofmorecomplexphasecontinuousmodulationtechniques,thecontroloftheoutputwaveformbecomesincreasinglymoredifficultwithanalogcircuitry.Inthesedesigns,usinganon-lineardigitaldesigneliminatestheneedforcircuitboardadjustmentsoveryieldandtemperature.AdigitaldesignthatmeetsthesegoalsisaDirectDigitalSynthesizerDDS.ADDSsystemsimplytakesaconstantreferenceclockinputanddividesitdownatoaspecifiedoutputfrequencydigitallyquantizedorsampledatthereferenceclockfrequency.ThisformoffrequencycontrolmakesDDSsystemsidealforsystemsthatrequireprecisefrequencysweepssuchasradarchirpsorfastfrequencyhoppers.Withcontrolofthefrequencyoutputderivedfromthedigitalinputword,DDSsystemscanbeusedasaPLLallowingprecisefrequencychangesphasecontinuously.Aswillbeshown,DDSsystemscanalsobedesignedtocontrolthephaseoftheoutputcarrierusingadigitalphasewordinput.Withdigitalcontroloverthecarrierphase,ahighspectraldensityphasemodulatedcarriercaneasilybegenerated.ThisarticleisintendedtogivethereaderabasicunderstandingofaDDSdesign,andanunderstandingofthespuriousoutputresponse.Thisarticlewillalsopresentasampledesignrunningat45MHzinahighspeedfieldprogrammablegatearrayfromQuickLogic.AbasicDDSsystemconsistsofanumericallycontrolledoscillator(NCO)usedtogeneratetheoutputcarrierwave,andadigitaltoanalogconverter(DAC)usedtotakethedigitalsinusoidalwordfromtheNCOandgenerateasampledanalogcarrier.SincetheDACoutputissampledatthereferenceclockfrequency,awaveformsmoothinglowpassfilteristypicallyusedtoeliminatealiascomponents.Figure1isabasicblockdiagramofatypicalDDSsystemdesign.ThegenerationoftheoutputcarrierfromthereferencesampleclockinputisperformedbytheNCO.ThebasiccomponentsoftheNCOareaphaseaccumulatorandasinusoidalROMlookuptable.AnoptionalphasemodulatorcanalsobeincludeintheNCOdesign.ThisphasemodulatorwilladdphaseoffsettotheoutputofthephaseaccumulatorjustbeforetheROMlookuptable.ThiswillenhancetheDDSsystemdesignbyaddingthecapabilitiestophasemodulatethecarrieroutputoftheNCO.Figure2isadetailedblockdiagramofatypicalNCOdesignshowingtheoptionalphasemodulator.FIGURE1:TypicalDDSSystem.FIGURE2:TypicalNCODesign.TobetterunderstandthefunctionsoftheNCOdesign,firstconsiderthebasicNCOdesignwhichincludesonlyaphaseaccumulatorandasinusoidalROMlookuptable.ThefunctionofthesetwoblocksoftheNCOdesignarebestunderstoodwhencomparedtothegraphicalrepresentationofEuler’sformulaejwt=cos(wt)+jsin(wt).ThegraphicalrepresentationofEuler’sformula,asshowninFigure3,isaunitvectorrotatingaroundthecenteraxisoftherealandimaginaryplaneatavelocityofwrad/s.Plottingtheimaginarycomponentversustimeprojectsasinewavewhileplottingtherealcomponentversustimeprojectsacosinewave.ThephaseaccumulatoroftheNCOisanalogous,orcouldbeconsidered,thegeneratoroftheangularvelocitycomponentwrad/s.Thephaseaccumulatorisloaded,synchronoustothereferencesampleclock,withanNbitfrequencyword.ThisfrequencywordiscontinuouslyaccumulatedwiththelastsampledphasevaluebyanNbitadder.TheoutputoftheadderissampledatthereferencesampleclockbyanNbitregister.WhentheaccumulatorreachestheNbitmaximumvalue,theaccumulatorrollsoverandcontinues.PlottingthesampledaccumulatorvaluesversustimeproducesasawtoothwaveformasshownbelowinFigure3.FIGURE3Euler’sEquationRepresentedGraphicallyThesampledoutputofthephaseaccumulatoristhenusedtoaddressaROMlookuptableofsinusoidalmagnitudevalues.Thisconversionofthesampledphasetoasinusoidalmagnitudeisanalogoustotheprojectionoftherealorimaginarycomponentintime.Sincethenumberofbitsusedbythephaseaccumulatordeterminesthegranularityofthefrequencyadjustmentsteps,atypicalphaseaccumulatorsizeis24to32bits.SincethesizeofthesinusoidalROMtableisdirectlyproportionaltotheaddressingrange,notall24or32bitsofthephaseaccumulatorareusedtoaddresstheROMsinusoidaltable.OnlytheupperYbitsofthephaseaccumulatorareusedtoaddressthesinusoidalROMtable,whereY<NbitsandYistypicallybutnotnecessarilyequaltoD,andDisthenumberofoutputmagnitudebitsfromthesinusoidalROMtable.SinceanNCOoutputsacarrierbasedonadigitalrepresentationofthephaseandmagnitudeofthesinusoidalwaveform,designershavecompletecontroloverfrequency,phase,andevenamplitudeoftheoutputcarrier.ByaddingaphaseportandaphaseaddertothebasicNCOdesign,theoutputcarrieroftheNCOcanbeMarrayphasemodulatedwhereMequalsthenumberofphaseportbitsandwhereMislessthanorequaltotheYnumberofbitsusedtoaddressthesinusoidalROMtable.ForsystemdesignsthatrequireamplitudemodulationsuchasQAM,amagnitudeportcanbeaddedtoadjustthesinusoidalROMtableoutput.NotethatthisportisnotshowninFigure2andthatthisfeatureisnotdemonstratedinthesampleQuickLogicFPGAdesign.Finally,frequencymodulationisagivenwiththebasicNCOdesign.Thefrequencyportcandirectlyadjustthecarrieroutputfrequency.SincefrequencywordsareloadedintotheDDSsynchronoustothesampleclock,frequencychangesarephasecontinuous.AlthoughDDSsystemsgivethedesignercompletecontrolofcomplexmodulationsynthesis,therepresentationofsinusoidalphaseandmagnitudeinanon-lineardigitalformatintroducesnewdesigncomplexities.Insamplinganycontinuous-timesignal,onemustconsiderthesamplingtheoryandquantizationerror.TounderstandtheeffectsofthesamplingtheoryonaDDSsystem,itisbesttolookattheDDSsynthesisprocessesinboththetimeandfrequencydomain.Asstatedabove,theNCOgeneratesasinusoidalwaveformbyaccumulatingthephaseataspecifiedrateandthenusesthephasevaluetoaddressaROMtableofsinusoidalamplitudevalues.Thus,theNCOisessentiallytakingasinusoidalwaveformandsamplingitwiththerisingorfallingedgeoftheNCOinputreferencesamplingclock.Figure4showsthetimeandfrequencydomainoftheNCOprocessing.Notethatthisrepresentationdoesnotassumequantization.Basedontheloadedfrequencyword,theNCOproducesasetofamplitudeoutputvaluesatasetperiod.Thefrequencydomainrepresentationofthissinusoidisanimpulsefunctionatthespecifiedfrequency.TheNCO,however,outputsdiscretedigitalsamplesofthissinusoidattheNCOreferenceclockrate.Inthetimedomain,theNCOoutputisafunctionofthesamplingclockedgestrobesmultipliedbythesinusoidwaveformproducingatrainofimpulsesatthesinusoidamplitude.Inthefrequencydomain,thesamplingstrobesofthereferenceclockproduceatrainofimpulsesatfrequenciesofKtimestheNCOclockfrequencywhereK=...-1,0,1,2....Sincethesamplingclockwasmultipliedbythesinusoidinthetimedomain,thefrequencydomaincomponentsofthesinusoidandthesamplingclockneedtobeconvolvedtoproducethefrequencydomainrepresentationoftheNCOoutput.ThefrequencydomainresultsaretheimpulsefunctionatthefundamentalfrequencyofthesinusoidandthealiasimpulsefunctionsoccurringatKtimestheNCOclockfrequencyplusorminusthefundamentalfrequency.Thefundamentalandaliascomponentoccurat:K*Fclk-FoutK*Fclk+FoutWhereK=...-1,0,1,2.....andK=0istheNCOsinusoidfundamentalfrequencyFoutisthespecifiedNCOsinusoidoutputfrequencyFclkistheNCOreferenceclockfrequencyFIGURE4NCOOutputRepresentationTimeandFrequencyDomainTheDACoftheDDSsystemtakestheNCOoutputvaluesandtranslatesthesevaluesintoanalogvoltages.Figure4showsthetimeandfrequencydomainrepresentationsoftheDACprocessingstartingwiththeNCOoutput.TheDACoutputisasampleandholdcircuitthattakestheNCOdigitalamplitudewordsandconvertsthevalueintoananalogvoltageandholdsthevalueforonesampleclockperiod.ThetimedomainplotoftheDACprocessingistheconvolutionoftheNCOsampledoutputvalueswithapulseofonesampleclockperiod.Thefrequencydomainplotofthesamplingpulseisasin(x)/xfunctionwiththefirstnullatthesampleclockfrequency.Sincethetimedomainwasconvolved,thefrequencydomainismultiplied.ThismultiplicationdampenstheNCOoutputwiththesin(x)/xenvelope.ThisattenuationattheDACoutputcanbecalculatedasfollowsandasampleoutputspectrumisshowninFigure5:Atten(F)=20log[(sin(pF/Fclk)/pF/Fclk)]WhereFistheoutputfrequencyFclkisthesampleclockfrequencyFIGURE5:DACOutputRepresentationinTimeandFrequencyDomainAsidefromthesamplingtheory,thequantizationoftherealvaluesintodigitalformmustalsobeconsideredintheperformanceanalysisofaDDSsystem.ThespuriousresponseofaDDSsystemisprimarilydictatedbytwoquantizationparameters.TheseparametersarethephasequantizationbythephaseaccumulatorandthemagnitudequantizationbytheROMsinusoidaltableandtheDAC.Asmentionedabove,onlytheupperYbitsofthephaseaccumulatorareusedtoaddresstheROMlookuptable.Itshouldbenoted,however,thatusingonlytheupperYbitsofthephaseaccumulatorintroducesaphasetruncation.Whenafrequencywordcontaininganon-zerovalueinthelower(N-Y-1:0)bitsisloadedintotheDDSsystem,thelowernon-zerobitswillaccumulatetotheupperYbitsandcauseaphasetruncation.Thefrequencyatwhichthephasetruncationoccurscanbecalculatedbythefollowing:Ftrunc=FW(N-Y-1:0)/2N-Y*Fclk.Aphasetruncationwillperiodically(attheFtruncrate)phasemodulatetheoutputcarrierforward2p/28tocompensateforfrequencywordgranularitygreaterthan2Y.Thephasejumpcausedbytheaccumulationofphasetruncatedbitsproducesspursaroundthefundamental.Thesespursarelocatedplusandminusthetruncationfrequencyfromthefundamentalfrequencyandthemagnitudeofthespurswillbe-20log(2Y)dBc.AsampleoutputofaphasetruncationspurisshowninFigure5.InatypicalNCOdesign,theROMsinusoidaltablewillholda?sinewave(0,p/2)ofmagnitudevalues.TheROMtableisgeneratedbytakingallpossiblephasevalueaddressesandmaptoarealmagnitudesinevalueroundedtothenearestDbits.Thus,themaximumerroroutputis±-?LSBgivingaworstcasespurof-20log(2D)dBc.LiketheNCOROMtable,aDACquantizesthedigitalmagnitudevalues.ADAC,however,outputsananalogvoltagecorrespondingtothedigitalinputvalue.WhendesigningtheNCOsinusoidalROMtable,oneshouldtakesomeempiricaldataontheDAClinearitytobetterunderstandtheinteractionbetweentheROMtableandtheDAC.ThequantizationforaDACisspecifiedagainstanideallinearplotofdigitalinputversusanalogoutput.Twolinearityparameters,differentialandintegrallinearity,areusedtospecifyaDAC’sperformance.Differentiallinearityistheoutputstepsizefrombittobit.ADACmustguaranteeadifferentiallinearityofamaximum1LSB.Whenaninputcodeisincreased,theDACoutputmustincrease.IftheDACvoltagedoesnotincreaseversusanincreasedigitalinputvalue,theDACissaidtobemissingcodes.Thus,a10bitDACthathasadifferentiallinearityofgreaterthat1LSBisonlyaccurateto9orlessbits.ThenumberofaccurateoutputbitswillspecifytheDDSspuriousperformanceas-20log(2dl)wheredlisthenumberdifferentiallinearbits..IntegrallinearityisameasureoftheDAC’soveralllinearperformanceversusanideallinearstraightline.Thestraightlineplotcanbeeithera“beststraightline”whereDCoffsetsarepossibleatboththeminandmaxoutputsoftheDAC,orthestraightlinecancrosstheendpointsoftheminandmaxoutputvalues.ADACwilltendtohaveacharacteristiccurvethatistraversedovertheoutputrange.Dependingontheshapeandsymmetry(symmetryaboutthehalfwaypointoftheDACoutput)ofthiscurve,outputharmonicsoftheDDSfundamentaloutputfrequencywillbeproduced.AstheseharmonicsapproachandcrosstheNyquistfrequencyofFclk/2,theharmonicsbecomeundersampledandreflectbackintothebandofinterest,0toFclk/2.ThisproblemisbestillustratedbysettingtheNCOoutputtoFclk/4plusaslightoffset.Thethirdharmonicwillfallminus3foldsthesmalloffsetfromthefundamentalandthesecondharmonicwillcrosstheNyquistfrequencyby2foldsthesmalloffsetleavingareflectedimagebackinthebandofinterestAsampleplotofthisfrequencysetupisshowninFigure5.OtherDACcharacteristicthatwillproduceharmonicdistortionisanydisruptionofthesymmetryoftheoutputwaveformsuchasadifferentriseandfalltime.ThesecharacteristicscantypicallybecorrectedbyboardcomponentsexternaltotheDACsuchasanRFtransformer,boardlayoutissues,attenuationpadsetc.GiventhecomplexitiesoftheDDSsystem,engineersshouldconsiderimplementingthedesignusingseparatedevicesforthenumericallycontrolledoscillator,thedigitaltoanalogconverter,andthelowpassfilter.Thisapproachallowsforsignalobservationatmanypointsinthesystem,yetiscompactenoughtobepracticalasanend-solution.Alternatively,thediscreteimplementationcanserveasaprototypingvehicleforasingle-chipmixedsignalASIC.TheauthordevelopedaversionofthedesignusingaHarrisHI5721evaluationboardfortheDAC.TheNCOattheheartoftheDDSdesign,andarandomgeneratortotestsignalmodulation,wasimplementedintoabout65%ofaQuickLogicfieldprogrammablegatearray(FPGA).ThisFPGA,aQL16x24B4000-gatedevice,waschosenforitshighperformance,ease-of-use,andpowerfuldevelopmenttools.TheNCOdesignincludedfollowing:DevelopedinVerilogwiththe8bitCLAadderschematiccapturedandnetlistedtoVerilog32bitfrequencywordinput32phaseaccumulatorpipelinedover8bits8bitphasemoudulationwordinput8bitsineROMlook-uptableThedesignwasdescribedmostlyinVerilog,withan8bitcarrylookaheadaddermodifiedfromQuickLogic’smacrolibrarynetlistedtoVerilog.Thewholedesigncyclewaslessthanfourdays(twodaystodescribethedesignandadayandahalftoprototypethehardware).Everythingworkedperfectlythefirsttime,withthedesignrunningatanimpressive45MHzaspredictedbythesoftwaresimulationtools.PlotsusedinthearticletoillustrateDDSperformanceparameterswereprovidedfromthetestconfiguration.Figure6belowshowstheexternalIOinterfacetotheNCOdesign.Thefunctionofeachsignalisdescribedinthefollowingtable.SignalFunctionTableFREQWORD[31:0]ThisinputisthefrequencycontrolwordtotheNCO.Thiswordcontrolsthephaseaccumulatorrate,andthus,theoutputfrequencyoftheDACOUTsinusoidalwaveform.Theoutputcarrierfrequencyiscalculatedbythefollowing:PHASEWORD[7:0]ThisinputisthephasemodulationcontrolwordtotheNCO.Thiswordcontrolsthephaseoffsetfollowingthephaseaccumulator.Thisphaseoffsetisusedtophasemodulatetheoutputcarrier.FWWRNThisinputisthelowassertedfrequencywordwritestrobe.ThisstrobeinputregisterstheFREQWORDinputontherisingedge.ThisstrobecanbeasynchronoustotheSYSCLK.SYSCLKThisisthereferencesystemclockinputtotheNCO.Thisclockisthesamplingclockoftheoutputcarrier.PNCLKThisinputisthepseudo-noisegeneratorclockinput.ThisclocksetsthedatarateoftheIandQdataoutputs.RESETNThisinputisalowassertedglobalreset.Whenasserted,theinternalphaseandfrequencywordregistersareclearedstoppingtheoutputcarrierat0radians.DACOUT[7:0]ThisoutputisthesinusoidalDACamplitudeword.ThiswordisvalidontherisingedgeoftheDACCLK.Thesinusoidalwaveformoutputisrepresentedbythefollowing:f(t)=sin(2pFout(t)+Pout)DACCLKThisoutputistheDACclockstrobe.ThisclockistheSYSCLKfeedbacktoanoutputpincompensatingforthelatencyoftheNCOIOpins.TheDACOUTamplitudewordswillbevalidontherisingedgeoftheDACCLK.SINThisoutputisasinglebitdigitalsinewaveoutput.ThissinewaveoutputcomesfromtheMSBofthephaseaccumulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinput.COSThisoutputisasinglebitdigitalcosinewaveoutput.ThiscosinewaveoutputcomesformtheMSBandnextmostsignificantbitofthephaseaccumulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinput.MSINThisoutputisasinglebitdigitalsinewaveoutput.ThissinewaveoutputcomesfromtheMSBofthephasemodulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinputandphaseoffsetbythephasewordinput.ThissinewaveoutputisthesameastheSINoutputwithaphaseoffsetofplus2p/28*PHASEWORD.MCOSThisoutputisasinglebitdigitalcosinewaveoutput.ThiscosinewaveoutputcomesformtheMSBandnextmostsignificantbitofthephasemodulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinputandthephaseoffsetbythephasewordinput.ThiscosinewaveoutputisthesameastheCOSoutputwithaphaseoffsetofplus2p/28*PHASEWORD.IDATAThisoutputisa25-1pseudonoiserandompattern.ThisoutputisnotafunctionalpartoftheNCOdesignbutusedtodemonstratephasemodulationusingthephaseport.QDATAThisoutputisa25-1pseudonoiserandompattern.ThisoutputisnotafunctionalpartoftheNCOdesignbutusedtodemonstratephasemodulationusingthephaseport.Figure6:TheExternalIOInterfaceTopLevel(dds.v)ThetopleveloftheNCOdesigninstantiatesthefunctionalblocksoftheNCOdesignandthePNgeneratorblock.PNGenerator(pngen.v)ThismoduleisnotpartoftheNCOdesignbutisusedtoproduceasamplerandomdatapatterntomodulatethecarrieroutput.ThismoduleusesthePNCLKinputtoclocktwoGoldcode5bitPNgenerators.TheoutputsofthePNgeneratorsareIDATAandQDATAoutputs.ThelowerlevelblockofthisNCOdesignconsistofasynchronousfrequencywordinputregister,asynchronousphasewordinputregister,a32bitpipelinedphaseaccumulator,an8bitphaseadder,andasinlockuptable.AdetaileddescriptionofeachoftheNCOblocksandthePNgeneratorareprovidedinthefollowingsections.LoadFrequencyWord(loadfw.v)Theloadfrequencywordblockisasynchronizingloadingcircuit.TheFREQWORD[31:0]inputdrivesathedatainputtothe32bitfwregregisterthatissampledontherisingedgeoftheFWWRNwritestrobe.TheFWWRNstrobealsodrivesthedatainputtoametastableflipflopfwwrnmthatisusedinconjunctionwithasynchronousregisterfwwrnstoproduceaFWWRNrisingedgestrobe.Thisrisingedgestrobeloadp1isthenpipedforanadditional3clockcyclesproducingtheloadstrobesloadp2,loadp3,andloadp4.Theloadstrobesareusedtosignalwhentoupdatethesynchronouspipeline8bitregisterspipefw1,pipefw2,pipefw3,andpipefw4tothesampledfrequencywordcontent.Thepipelineregistersareconcatenatedtoproducethe32bitsynchronousfrequencywordoutputSYNCFREQ[31:0]thatisstaggeredtocompensateforthe32bitpipelinedphaseadder.PhaseWordAccumulator(phasea.v)Thephaseaccumulatorblockisa32bitaccumulatorthatispipelinedin8bitsections.ThismoduleinstanciatesaschematiccapturedcarrylockaheadCLAadderthathasacarryinandcarryoutport.Thesynchronousfrequencyword,staggeredtomatchthepipelinedaccumulator,isloadedintotheBinputoftheCLAadders.ThesumoutputoftheCLAaddersareregisteredinthepiperegisteredwiththeoutputtiedbacktotheAinputoftheCLAadders.ThecarryoutputoftheCLAaddersisregisteredinthepipecregisterswiththeoutputtiedtothenextmostsignificantCLAaddercarryinput.Themostsignificantsumoutputregisterpipe4isassignedtothePHASEoutputportgivingaphasevaluequantizedto8bits.Adigitalsineandcosinevalueisalsocalculatedfromthepipe4registerandbroughtoutofthechipasSINandCOS.LoadPhaseWord(loadpw.v)Theloadphasewordblockisasynchronizingloadingcircuit.ThePHASEWORD[7:0]inputdrivesthedatainputtothe32bitpwregregisterthatissampledontherisingedgeofthePWWRNwritestrobe.ThePWWRNstrobealsodrivesthedatainputtoametastableflipfloppwwrnmthatisusedinconjunctionwithasynchronousregisterpwwrnstoproduceaFWWRNrisingedgestrobe.Thisrisingedgestrobeloadisusedtosignalwhentoupdatethesynchronousphasewordregisterphswd.ThephswdregisterisassignedtothesynchronousphasewordoutputSYNCPHSWD[7:0].PhaseModulator(phasemod.v)Thephasemodulatorblockisusedtophaseoffsetthephaseaccumulator8bitquantizedoutputwiththesynchronousphasewordfromtheloadphasewordblock.ThismoduleinstantiatesaCLAadderwiththeAinputtiedtothesynchronousphaseoutputandtheBinputtiedtothephaseaccumulatoroutput.ThesumoutputoftheadderisregisteredinthemphsregregisterandassignedtotheMODPHASEoutputport.AmodulatedversionofthesineandcosinevaluesarecalculatedandbroughtoutofthechipasMSINandMCOS.SineLockup(sinlup.v)Thismoduletakesthemodulatedphasevalueformthephasemodulatorblockandtranslatedthequantized8bitvalueintoasinewaveformamplitudevaluequantizedto8bits.ThetranslationfromphasetoamplitudeisperformedbyasineROMtablethatininstantiatedinthismodule.TheROMtableisreducedtoa?ofthesymmetricalsinewaveformandtheMSBofthesinewaveformisequivalenttothemodulatedphaseinput.Thismoduleperformsthecalculationstoreconstructacompleteperiodofthesinewaveformfromthe?representationoftheROMtableandtheMSBofthemodulatedphaseinput.Tobetterunderstandtheprocessingofthismodule,considerthefollowing.Themodulatedphasevalueisa0to2pvaluequantizedto8bits2p/28.Thequantizedvalueforp/2,p,3p/2,and2pare0x3F,0x7F,0xBF,and0xFF.Theamplitudevaluesfor0top/2isstoredintheROMtable.Theamplitudevaluesforp/2toparetheROMtableoutputinthereverseorder.Theamplitudevaluesforpto3p/2arethesameoutputastheamplitudevaluefrom0top/2withtheoutputfromtheROMtableinverted.Finallytheamplitudevaluefor3p/2to2parethesameasforpto3p/2withtheROMtableaccessedinreverse.ThismodulemanagestheaddressvaluestotheROMtableandtheamplitudeoutputstoformthecompleteperiodofthesinewaveform.ThefirstprocessofgeneratingthesinewavefunctionistheaddressingoftheROMtablesuchthatphaseanglesp/2topand3p/2to2pareaddressedinthereverseorder.ReverseaddressingisaccomplishedbysimplyinvertingtheROMtableaddressinputvector.ThephasemodulatedaddressinputisinvertedwhentheMODPHASE[6]isoneandisthenregisteredinthephaseaddregister.ThephaseaddressisusedtoaddresstheROMsinetablewiththeoutputregisteredintheqwavesin_ffregister.Toconstructthenegativeamplitudevaluesofthesinewaveform,theMSBofthemodulatephasewordinputisregisteredtwiceinmodphase_msb1_ffandmodphase_msb2_ff,compensatingforthetwocyclelatencyofthephaseaddandqwavesin_ffregisters.ThedelayedMSBbitisusedtoinverttheROMtableoutputwhenone.ThealteredROMtableoutputandtheinvertofthedelayedmodulatedphasewordMSBarefinallyregisteredinbythedac_ffregisterandthenassignedtotheDACOUToutputport.SineROMTable(romtab.v)ThismoduleisthesinewaveformROMtable.Thistableconvertsthephasewordinputtoasineamplitudeoutput.Toconservearea,only?ofthesymmetricalsinewaveformisstoredintheROM.Thesinevaluesstoredinthistablearethe0top/2unsignedvaluesquantizedto8bits.Thus,theROMtablerequiresa6bitphaseaddressinputandoutputsa7bitamplitudeoutput.Thesinlupmoduleprocessesthephaseandamplitudevaluestoproduceacompletesineperiod.DanMorellihasover9yearsofdesignandmanagementexperience.Hisareasofexpertiseincludespreadspectrumcommunications(involvingGPS,TDRSS,and802.11),PCchipsetandsystemarchitecture,celllibrarydevelopment(forECLdevices)andASICdevelopment.Hehasbeenpublishedandhasmultiplepatentsawardedandpending.DancurrentlyworksforAccelentSystemsInc.,anelectronicdesignconsultingcompany,whereheisafounderandtheVPofEngineering.

數(shù)字頻率合成器在探討許多復雜的相位連續(xù)的調(diào)制技術中，對模擬電路中輸出波形的控制已經(jīng)越來越困難。在這些設計中，使用非線性數(shù)字式設計除去電路板需要的調(diào)整額外輸出和溫度。一個適合這個目標的數(shù)字式設計就是直接數(shù)字頻率合成器（DDS）。一個DDS系統(tǒng)僅僅使用一個恒定參考時鐘輸入和將該時鐘分解為指定的量化數(shù)位頻率輸出或者對參考時鐘頻率取樣。這種形式是頻率控制使得DDS系統(tǒng)成為需要精確頻率掃描比如雷達尖叫聲或者快速頻率計量器的理想系統(tǒng)。根據(jù)數(shù)字輸入控制字以控制輸出頻率，DDS系統(tǒng)可以用來當作一個允許精確頻率連續(xù)改變相位的鎖相環(huán)（PLL）。根據(jù)后面的說明，我們知道DDS系統(tǒng)還可以使用輸入數(shù)字相位控制字來控制輸出載波的相位。用數(shù)字式控制載波相位，很容易產(chǎn)生一個高頻譜密度的相位調(diào)制載波。本文主旨是給讀者一個基本的DDS設計和寄生輸出響應的知識。本文將展示一個運行于45MHz的快速現(xiàn)場可編輯邏輯器件。一個基本的DDS系統(tǒng)包括一個數(shù)字振蕩器（NCO）用來產(chǎn)生輸出載波，和一個數(shù)模轉換器（DAC）用來將從NCO過來的數(shù)字式正弦曲線字產(chǎn)生一個抽樣的模擬載波。當DAC的輸出是根據(jù)參考時鐘頻率的抽樣時，通常用一個圓滑波形的低通濾波器來消除混疊成分。根據(jù)輸入的參考時鐘抽樣經(jīng)過NCO來產(chǎn)生輸出載波。NCO的基本構成是一個相位累加器和一個正弦ROM查找表。通過增加NCO的載波相位調(diào)制的輸出能力可以提高DDS系統(tǒng)的設計。為了更好的理解NCO設計的各種功能，首先考慮僅包括一個相位累加器和一個正弦ROM查找表的基本NCO設計。與歐拉公式（Euler’sformula）圖解比較就能最好地理解這兩個表的NCO設計的功能。歐拉公式的圖解如圖3所示，是一個單位向量繞著實軸和虛平面的中心以Wrad/s的速度轉圈。這個頻率控制字是最后一個抽樣相位值通過一個N位加法器的連續(xù)地累加而成。加法器的輸出是參考抽樣時鐘通過一個N位寄存器的抽樣。當累加器達到N位最大值的時候，累加器翻轉然后繼續(xù)。然后相位累加器的抽樣輸出用來在一個正弦量化值表里進行查找。抽樣相位到正弦量化的轉化可以看作是真實的或者虛擬的成分及時地影射。因為相位累加器的比特位數(shù)決定了頻率調(diào)整的步進，一個典型的相位累加器的大小是24到32位。由于正弦ROM表的大小是跟尋址范圍直接成比例的，因此，不是所有相位累加器的24或32位都用來作為正弦ROM表的地址。僅是相位累加器的高Y（Y〈N〉位是用來作為正弦ROM表的地址，Y通常不必要等于正弦ROM表的輸出量位D。因為一個NCO輸出的一個基于一個數(shù)字表示的相位和正弦波量化形式的載波，所以設計者可以完全的控制輸出載波的頻率，相位和幅度。通過加入一個相位端口和一個相位加法器到一個基本的NCO設計中，NCO的輸出載波當M等于相位端口數(shù)和M小于或等于Y（用來作為正弦ROM表的地址位數(shù)）時可以被M矩陣相位調(diào)制。假如系統(tǒng)設計需要幅度調(diào)制如QAM，可以加入一個量化端口來調(diào)整正弦ROM表的輸出。注意到這個端口沒有在圖2里表示出來以及這個特色沒有在簡單的快速邏輯FPGA設計中論證。最后，頻率是調(diào)制是一個基本的NCO設計給出的。因為頻率控制字是跟抽樣時鐘是同步裝載到DDS的，頻率的轉化是相位連續(xù)的。雖然DDS系統(tǒng)給設計者完全地控制復雜的調(diào)制合成，但是在一個非線性數(shù)字格式的正弦相位和量級的表示卻是復雜的新設計。在取樣任何的連續(xù)時間信號時，必須考慮取樣原理和量子化誤差。為了理解DDS系統(tǒng)中取樣理論的效果，最好看一下時間和頻率域的DDS合成過程。就象上面規(guī)定的，通過以指定的速率累積的形式由NCO產(chǎn)生一個正弦波然后用一個相位的值來定位一個正弦調(diào)制ROM表的值。因此，NCO本質(zhì)上用一個正弦波和用NCO的上升或下降沿輸出參考取樣時鐘對其取樣。圖4表示在時間和頻率域里NCO的處理。注意到這個表示并非量子化假設?；陬l率控制字的裝載，NCO在一個時期內(nèi)提供一批幅度的輸出值。這個正弦曲線的頻率域表示在指定的頻率里是一個推動的作用。N