第5章 時(shí)序狀態(tài)機(jī)設(shè)計(jì)

第5章時(shí)序狀態(tài)機(jī)設(shè)計(jì)第5章時(shí)序狀態(tài)機(jī)設(shè)計(jì)21有限狀態(tài)機(jī)狀態(tài)機(jī)設(shè)計(jì)實(shí)例5.1有限狀態(tài)機(jī)

有限狀態(tài)機(jī)及其設(shè)計(jì)技術(shù)是數(shù)字系統(tǒng)設(shè)計(jì)中的重要組成部分，是實(shí)現(xiàn)高效率、高可靠和高速控制邏輯系統(tǒng)的重要途徑。有限狀態(tài)機(jī)FSM（FiniteStateMachine），其在任意時(shí)刻都處于有限狀態(tài)集合中的某一種狀態(tài)。有限狀態(tài)機(jī)是指輸出取決于過去輸出部分和當(dāng)前輸入部分的時(shí)序邏輯電路。有限狀態(tài)機(jī)又可以認(rèn)為是組合邏輯和寄存器邏輯的一種組合。狀態(tài)機(jī)特別適合描述那些發(fā)生有先后順序或者有邏輯規(guī)律的事件，其實(shí)這就是狀態(tài)機(jī)的本質(zhì)。狀態(tài)機(jī)就是對(duì)具有邏輯順序或時(shí)序規(guī)律的事件進(jìn)行描述的一種方法。5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例1．穆爾型狀態(tài)機(jī)設(shè)計(jì)實(shí)例“1101”序列檢測(cè)器【例5.2-1】

穆爾型狀態(tài)機(jī)的VerilogHDL三always塊描述實(shí)例。modulemoore(inputclk,inputrst,inputdin,outputregdout);5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例parameters0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;//狀態(tài)說明reg[2:0]present_state,next_state; //現(xiàn)態(tài)、次態(tài)//狀態(tài)模塊always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end//次態(tài)always@(*)begincase(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)next_state<=s4;elsenext_state<=s0;s4:if(din==0)next_state<=s0;elsenext_state<=s2;default:next_state<=s0;endcaseendalways@(*)beginif(present_state==s4)dout<=1;elsedout<=0;endendmodule5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例【例5.2-2】穆爾型狀態(tài)機(jī)的Testbench仿真測(cè)試。5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例2．米利型狀態(tài)機(jī)設(shè)計(jì)實(shí)例“1101”序列檢測(cè)器【例5.2-3】米利型狀態(tài)機(jī)的VerilogHDL三always塊描述實(shí)例。modulemealy(inputclk,inputrst,inputdin,outputregdout);5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]present_state,next_state;//狀態(tài)模塊always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end//次態(tài)模塊always@(*)begincase(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)next_state<=s1;elsenext_state<=s0;default:next_state<=s0;endcaseend//輸出模塊always@(*)beginif((present_state==s3)&&(din==1))dout<=1;elsedout<=0;endendmodule5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例【例5.2-4】米利型狀態(tài)機(jī)的VerilogHDL雙always塊描述實(shí)例。modulemealy(inputclk,inputrst,inputdin,outputregdout);parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]present_state,next_state;//狀態(tài)模塊always@(posedgeclkorposedgerst)beginif(rst)present_state=s0;elsepresent_state=next_state;end5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例//次態(tài)和輸出模塊always@(*)begindout<=0;case(present_state)s0:if(din==1)next_state<=s1;elsenext_state<=s0;s1:if(din==1)next_state<=s2;elsenext_state<=s0;s2:if(din==0)next_state<=s3;elsenext_state<=s2;s3:if(din==1)beginnext_state<=s1;dout<=1;endelsenext_state<=s0;default:next_state<=s0;endcaseendendmodule5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例【例5.2-5】米利型狀態(tài)機(jī)的VerilogHDL單always塊描述實(shí)例。modulemealy(inputclk,inputrst,inputdin,outputregdout);parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;reg[1:0]state;//狀態(tài)模塊always@(posedgeclkorposedgerst)beginif(rst)beginstate=s0;dout<=0;end5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例elsebegindout<=0;case(state)s0:if(din==1)state<=s1;elsestate<=s0;s1:if(din==1)state<=s2;elsestate<=s0;s2:if(din==0)state<=s3;elsestate<=s2;s3:if(din==1)beginstate<=s1;dout<=1;endelsestate<=s0;default:state<=s0;endcaseendendendmodule5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例米利型狀態(tài)機(jī)的Testbench仿真測(cè)試米利型狀態(tài)機(jī)仿真：?jiǎn)蝍lways塊描述5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例【例5.2-6】狀態(tài)機(jī)描述實(shí)例，A是輸入，X是穆爾型輸出，Y是米利型輸出。modulemealy_moore( inputclk, inputrst_n, inputa, outputregx,y ); parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;

reg[1:0]present_state,next_state; //狀態(tài)模塊 always@(posedgeclkornegedgerst_n)begin if(!rst_n)present_state<=s0;//在rst_n下降沿設(shè)s0為初態(tài) elsepresent_state<=next_state; end

5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例//第二個(gè)always是將present_state和輸入a作為敏感變量 always@(present_stateora)begin

case(present_state)

s0:begin

x<=0;y<=0;

next_state<=(a==1)?s2:s0; end s1:begin

x<=1;

if(a==0)begin

y<=1;next_state<=s0;

end elsebegin

y<=0;

next_state<=s1;

end

end5.2狀態(tài)機(jī)設(shè)計(jì)實(shí)例 s2:begin

x<=0;

if(a==0)begin

y<=1;

next_state<=s0;

end elsebegin

y<=0;

next_state<=s3;

end

end s3:begin

x<