大規(guī)模集成電路習(xí)題與答案

電路性能：PROBLEM1.Consideranisolated2mmlongand1μmwideM1(Metal1)wireoverasiliconsubstratedrivenbyaninverterthathaszeroresistanceandparasiticoutputcapccitance.Howwillthewiredelaychangeforthefollowingcases?Explainyourreasoningineachcase.a.Ifthewirewidthisdoubled.b.Ifthewirelengthishalved.c.Ifthewirethicknessisdoubled.d.IfthicknessoftheoxidebetweentheM1andthesubstrateisdoubled.PROBLEM2.Atwo-stagebufferisusedtodriveametalwireof1cm.ThefirstinverterisofminimumsizewithaninputcapacitanceCi=10fFandaninternalpropagationdelaytp0=50psandloaddependentdelayof5ps/fF.Thewidthofthemetalwireis3.6μm.Thesheetresistanceofthemetalis0.08Ω,thecapacitancevalueis0.03fF/μm2a.Whatisthepropagationdelayofthemetalwire?b.Computetheoptimalsizeofthesecondinverter.Whatistheminimumdelaythroughthebuffer?PROBLEM3.AnNMOStransistorisusedtochargealargecapacitor,asshownthefollowingFigure.Theminimumsizedevice,(0.25/0.25)forNMOSand(0.75/0.25)forPMOS,hastheonresistance35kΩ.a.DeterminethetpLHofthiscircuit,assuminganidealstepfrom0to2.5Vattheinputnode.b.AssumethataresistorRSof5kΩisusedtodischargethecapacitancetoground.DeterminetpHL.c.TheNMOStransistorisreplacedbyaPMOSdevice,sizedsothatkpisequaltotheknoftheoriginalNMOS.Willtheresultingstructurebefaster?Explainwhyorwhynot.PROBLEM4．ThefigurebelowassemblesaRTLcircuitwheretheactivedeviceisaNMOStransistorwhichhasaresistiveload.AssumetheswitchmodelbehavioroftheNMOStransistor.WhenVin<1.25V,theresistanceofthetransistorisinfinite.WhenVin≥1.25V,thetransistorcanbemodeledashavingaresistanceof150ohms.A.DeterminethevaluesforVOHandVOL.Explainyouranswer.B.CalculatetpLHandtpHLtoobtaintheaveragepropagationdelay,tp.Solution:PROBLEM5.ThenextfigureshowstwoimplementationsofMOSinverters.ThefirstinverterusesonlyNMOStransistors.a.CalculateVOH,VOL,Vthforeachcase.b.FindVIH,VIL,NMLandNMHforeachinverterandcommentontheresults.Howcanyouincreasethenoisemarginsandreducetheundefinedregion?0.25umCMOS工藝(L=Lmin)MOS管參數(shù)Problem6:WewanttodesignaminimumsizedCMOSinverterwith0.25umprocess(=0.12um).TheminimumsizedNMOStransistor’slayersarelistedandshownbelowinFigurebelow.A.Determineandlistthefollowing:MinimumTransistorLengthMinimumTransistorWidthMinimumSource/DrainAreaMinimumSource/DrainPerimeter Pleaselistthedesignrulesyoucomeacrossthatleadtoyourresults.polypolygatenfetcantactndifB.WedesiretheminimumsizedCMOSinverterwithasymmetricalVTC(VTh=VDD/2)inthe0.25umtechnology.Calculatethefollowingforthepull-upPMOStransistorinthedesign.a.MinimumTransistorLengthb.MinimumTransistorWidthc.MinimumSource/DrainAread.MinimumSource/DrainPerimeter Assumethefollowing: VDD=2.5V,andrefertothetablesinthebelow.C.UsingthesameminimumsizeinverterfrompartB,determinetheinputcapacitance(i.e.theloaditpresentswhendriven)andthetotalloadcapacitancethattheinverterpresents.D.CalculatetpLHandtpHLtoobtaintheaveragepropagationdelay,tp.Rulesare:MinimumAnswer:A:a.L=b.W=c.LdrainAD=AS=0.48*0.6um=0.288um2d.PD=PS=0.6um*2+0.48um=1.68umB:查表得出一下參數(shù)：VT0p=-0.43VVT0n=0.4VKn’=115×10-6A/V2Kp’=30×10-6A另：L=0.24um,Wn=0.48um帶入上述公式計(jì)算得出：KR=0.965WpWeassumeunpandcancalculateWp=1.907μmAD=1.907μm*0.6μm=1.1442μm2PD=2*0.6μm+1.2μm=3.107μmC:NMOS: Cgn=CoxLnWn=0.6912fFNMOS管襯底接0V，輸出從1→0(V12=-1.25V)：輸出從0→1(V1=0V變?yōu)閂2=-1.25V)：PMOS:Cgp=CoxLpWp)=2.74608fFPMOS管襯底接2.5V，輸出從1→0(V1=0V變?yōu)閂2=-1.25V)：輸出從0→1(V12=-2.5V)：如果m以0.5計(jì)算：NMOS管襯底接0V，輸出從1→0(V12=-1.25V)：輸出從0→1(V1=0V變?yōu)閂2=-1.25V)：PMOS管襯底接2.5V，輸出從1→0(V1=0V變?yōu)閂2=-1.25V)：輸出從0→1(V12=-2.5V)：D：Cload計(jì)算：Cload=Cwire+Cg+Cgd,n+Cgd,p+Cdb,n+Cdb,p≈Cg+Cdb,n+Cdb,pCg=Cgn+Cgp=0.6912+2.74608=3.43728fF輸出從1→0(V1=0V變?yōu)閂2=-1.25V)：Cload≈Cg+Cdb,n+Cdb,p=6.3578326fF輸出從0→1(V12=-2.5V)：Cload≈Cg+Cdb,n+Cdb,p=6.0347782fF如果以m=0.5，那么：輸出從1→0(V1=0V變?yōu)閂2=-1.25V)：Cload≈Cg+Cdb,n+Cdb,p=6.2915162fF輸出從0→1(V12=-2.5V)：Cload≈Cg+Cdb,n+Cdb,p=5.8929732fFPROBLEM7．WewanttodesignaminimumsizedCMOSinverterwith0.25umprocess(=0.12um)anddesiretheinverterwithasymmetricalVTC(VTh=VDD/2).TheminimumsizedNMOStransistor’slayersareshownasproblem6.Assumethefollowing:VDDV,andrefertothetablesinthebelow.A.Determinetheinputcapacitance(i.e.theloaditpresentswhendriven)andthetotalloadcapacitancethattheinverterpresents.B.CalculatetpLHandtpHLtoobtaintheaveragepropagationdelay,tp.PROBLEM8.Sizingachainofinverters.a.Inordertodrivealargecapacitance(CL=20pF)fromaminimumsizegate(withinputcapacitanceCi=10fF),youdecidetointroduceatwo-stagedbufferasshowninthefollowingfigure.Assumethatthepropagationdelayofaminimumsizeinverteris70ps.Alsoassumethattheinputcapacitanceofagateisproportionaltoitssize.Determinethesizingofthetwoadditionalbufferstagesthatwillminimizethepropagationdelay.b.Ifyoucouldaddanynumberofstagestoachievetheminimumdelay,howmanystageswouldyouinsert?Whatisthepropagationdelayinthiscase?c.Describetheadvantagesanddisadvantagesofthemethodsshownin(a)and(b).PROBLEM9.ConsideraCMOSinverterwiththefollowingparameters:VT0,n=1.0VVT0,p=-1.2VμnCox=45uA/V2μpCox=25uA/V2(W/L)n=10(W/L)p=20Thepowersupplyvoltageis5V,andtheoutputloadcapacitanceis1.5pF.a.Calculatetherisetimeandthefalltimeoftheoutputsignalusingaveragecurrentmethod.b.Determinethemaximumfrequencyofaperiodicsquare-waveinputsignalsothattheoutputvoltagecanstillexhibitafulllogicswingfrom0Vto5Vineachcycle.c.Calculatethedynamicpowerdissipationatthisfrequency.d.Assumethattheoutputloadcapacitanceismainlydominatedbyfixedfan-outcomponent(whichareindependentofWnandWp).Wewanttore-designtheinvertersothatthepropagationdelaytimesarereducedby25%.DeterminetherequiredchanneldimensionsofthenMOSandthepMOStransistors.Howdoesthisre-designinfluencetheswitching(inversion)threshold?PROBLEM10.ConsiderthefollowinglowswingdriverconsistingofNMOSdevicesM1andM2.AssumethattheinputsINandIN’havea0Vto2.5VswingandthatVIN=0VwhenVIN’=2.5Vandvice-versa.AlsoassumethatthereisnoskewbetweenINandIN’(i.e.,theinverterdelaytoderiveINfromINiszero).a.WhatvoltageisthebulkterminalofM2connectedto?b.Whatisthevoltageswingontheoutputnodeastheinputsswingfrom0Vto2.5V.Showthelowvalueandthehighvalue.c.AssumethattheinputsINandINhavezeroriseandfalltimes.AssumeazeroskewbetweenINandIN’.Determinethelowtohighpropagationdelayforchargingtheoutputnodemeasuredfromthethe50%pointoftheinputtothe50%pointoftheoutput.Assumethatthetotalloadcapacitanceis1pF,includingthetransistorparasitics.MOS管參數(shù)參照題4。LogicStyles:Problem1:Considerthecircuitoffollowing.a.WhatisthelogicfunctionimplementedbytheCMOStransistornetwork?SizetheNMOSandPMOSdevicessothattheoutputresistanceisthesameasthatofaninverterwithanNMOSW/L=4andPMOSW/L=8.Solution:b.WhataretheinputpatternsthatgivetheworstcasetpHLandtpLH.Stateclearlywhataretheinitialinputpatternsandwhichinput(s)hastomakeatransitioninordertoachievethismaximumpropagationdelay.Considertheeffectofthecapacitancesattheinternalnodes.Solution:TheworstcasetpHLhappenswhentheinternalnodecapacitances(Cx2andCx3)arechargedbeforethehightolowtransition.Theinitialstatesthatcancausethisare:ABCD=[1010,1110,0110].Thefinalstateisoneof:ABCD=[1011,0111].TheworstcasetpLHhappenswhenCx1isdischargedbeforethelowtohightransition.Theinputpatternthatcancausethisis:ABCD=[0111]=>[0011].Problem2:Acomplexlogicgateisshowninthefollowing.a.WritetheBooleanequationsforoutputsFandG.Whatfunctiondoesthiscircuitimplement?Solution:b.Whatlogicfamilydoesthiscircuitbelongto?Solution:CVSLProblem3:LogicStylesa.Whatisthefunctionofthecircuitinthisfigure?Solution:??b)Whatisthelogicfunctionperformedbythedynamicgateshownbelow?Solution:c)WhatisthelogicfunctionofthefollowingDynamicgate?Solution:d)WhatisthelogicfunctionofthefollowingCPLgate?Solution:Problem4:LogicStylesa)ImplementthefunctionwithacomplexstaticCMOSgate.YoushouldarrangeyourgatetominimizethedelayfromtheEinput,andsothattheworst-casepullupresistanceisequaltotheworst-casepulldownresistance.Solution:不只一種答案b)Designa4inputmultiplexer(seethetruth-tablebelowforitsfuction)inthecomplementarypass-transistorlogicstyleusingaminimumnumberoftransistors.Solution:Problem5:Sequentialcircuits.a)Wouldthesequentialcircuitfromthefigureabovebeconsideredalatch,amaster-slavelatchpairorapulse-triggeredlatch?Brieflyexplainyouranswer.Solution:b)Drawthetimingwaveformsforthiscircuit.c)Redesignthiscircuit,suchthatitalsoimplementsanORfunctionoftheinputs.Problem6:Sequentialcircuits.a)Wouldthesequentialcircuitfromthefigureabovebeconsideredalatch,amaster-slavelatchpairorapulse-triggeredlatch?Brieflyexplainyouranswer.b)Alltransistorsinthiscircuitareunit-sized,withequivalentresistancesRandgatecapacitancesC(ignorediffusioncapacitances).CalculatethepropagationdelaytClk-Qforhigh-to-lowandlow-to-hightransitions.LoadontheoutputQisequal12CSolution:Apulse-triggeredlatchProblem7:SequentialElementsInthisproblemwewillbeexaminingthelatchshownbelow,whichhasbeenimplementedoutofatri-stateinverter.Throughoutthisproblem,youcanassumethatVDD=2.5V,CG=2fF/μm,CD=2fF/μm,andRsqn=Rsqp/2=15k?/□.a)Assumingthelatchisideal(i.e.,hasnodelay,zerosetup/holdtime,etc),fillinthewaveforgiventheclockandinputsshownbelow.Solution:b)ForCL=50fFandassumingisinitiallychargedtoVDDandyisinitially0V,whatisthetclk-qofthislatchwhenD=1?Youshouldassumethatclkisaramp.Solution:tclk-q=c)OneofyourfellowdesignerscomestoyouonedayandsaysthatwhensheusedthislatchinhercircuitwithCL=5fF,thelatchfailedtofunctioncorrectly.Morespecifically,ifDtransitioned,theinverterreceivingtheoutputofthelatchwouldtransitionevenwhenclkwaslow.However,youhaveverifiedthatthelatchfunctionscorrectlywhenCL=50fF.WhatisthecauseoftheerrorwhenthelatchhasasmallCL?(Hint:ThinkaboutthesecondtransitionofD)Solution:Chargeshared)Whatistheminimumloadcapacitancerequiredforthelatchtofunctioncorrectly?YoucanassumethattheinverterreceivingtheoutputofthelatchhasanidealVTCwithaswitchpointVth=VDD/2,andthatnoneofthetransistors’source/drainregionshavebeenshared.Solution:CL>12fFe)OtherthanartificiallyincreasingCL,howcanyoumodifythelatchtofixtheproblemyouidentifiedinpartc)?Youshouldexplainyourfixanddrawanewtransistor-levelschematicofthelatch(nosizingnecessary).(Notethatthereismorethanonepossiblefix–youwillreceivebonuscreditforuptotwoadditionalfixesyouidentifyanddraw.)Solution:Problem8:SequentialElementsSolution:Solution:Designforspeed:Problem1.Adominobufferisshownabove.Alltransistorsaresizedatminimumlength.Thewidthsofthetransistorshavebeenlabeledonthediagram.Capacitancescanbecalculatedas2fF/um.VDD=2.5V.Findthelogicaleffortofthisdominobufferduringtheevaluationphase.Solution:.AssumetheoutputnodeisconnectedtoaloadCL=50fF.Calculatethedelay(duringtheevaluationphase)frominputtooutputintermsoftp0,theintrinsicdelayofaminimumsymmetricallysizedinverter.Solution:.AkeeperPMOSisM4addedtothecircuitasshownbelow.FindthemaximumsizeofM4forproperoperationofthisdominobuffer.Youcanignorebodyeffect.Usetheparametersasbelow.Solution:M1andM3areinseries.Theycanbecombinedintoanequivalent1umwideNMOStransistor.Toguaranteetheproperoperationofthisdominobuffer,M1andM3shouldbeabletopulltheintermediatenodexbelowVTn.(ItisalsookifstudentsassumexispulledbelowVMoftheskewedinverter,thoughitissafertopullxbelowVTn.)Assumex=VTn.AcurrentequationcanbesetuptofindoutthemaximumsizeoftheM4..Problem2.AssumetheinvertersareimplementedinstandardCMOSwithsymmetricalVTC.Furthermore,assumeCintrinsic=Cgate.Equivalentresistanceandinputcapacitanceofunit-sizedinverterareRandC,respectively.SizingfactorS≥1.a.ForinvertersinFig.2a,pickthebestsizingfactorsS2andS3tominimizepropagationdelay.Whatistheminimumdelay(tp0isthedelayofunit-sizedinverter)?Solution:S2=3,S3=9tp=3tp,stage=3tp0·(1+fopt)=12tp0(1pt)b.Whatisthedelay(intermsoftp0)ofthecircuitinFig.2b?Solution:tptp0c.AssumeyoucanchoosethesizingS2andS4forinvertersinFig.2c.Whataretheoptimalvaluesforminimumdelay?Whatisthedelay(expressedintermsoftp0)?Solution:Datapath—Adders:PROBLEM1.ForthisproblemyouaregivenacelllibraryconsistingoffulladdersandtwoinputBooleanlogicgates(i.e.AND,OR,INVERT,etc.).a.DesignanN-bittwo'scomplementsubtracterusingaminimalnumberofBooleanlogicgates.Specifythevalueofanyrequiredadditionalsignals(e.g.,Cin).b.ExpressthedelayofyourdesignasafunctionofN,tcarry,tsum,andtheBooleangatedelays(tand,tor,tinv,etc.).PROBLEM2.ThecircuitofFigure0.2implementsa1-bitdatapathfunctionindynamic(precharge/evaluate)logic.a.WritedowntheBooleanexpressionsforoutputsFandG.OnwhichclockphasesareoutputsFandGvalid?b.Towhatdatapathfunctioncouldthisunitbemostdirectlyapplied(e.g.,addition,subtraction,comparison,shifting)?PROBLEM3.ConsiderthedynamiclogiccircuitofFigure0.2.a.WhatisthepurposeoftransistorM1?Isthereanotherwaytoachievethesameeffect,butwithreducingcapacitiveloadingontheclockF?b.HowcantheevaluationphaseofFbespedupbyrearrangingtransistors?Notransistorsshouldbeadded,deleted,orresized.c.CantheevaluationofGbespedupinthesamemanner?Whyorwhynot?PROBLEM4.Figure0.4showsapopularadderstructurecalledtheconditional-sumadder.Figure0.4.ashowsafour-bitinstanceoftheadder,while0.4.bgivestheschematicsofthebasicaddercell.Noticethatonlypass-transistorsareusedinthisimplementation.a.DeriveBooleandescriptionsforthefouroutputsoftheone-bitconditionaladdercell.b.Basedontheresultsofdescribehowtheschematico