89S52系列微控制器中英文對(duì)照外文翻譯文獻(xiàn)

中英文對(duì)照外文翻譯文獻(xiàn)(文檔含英文原文和中文翻譯)89S52seriesmicrocontrollerThe89S52familyofmicrocontrollersisbasedonanarchitecturewhichishighlyoptimizedforembeddedcontrolsystems.ItisusedinawidevarietyofapplicationsfrommilitaryequipmenttoautomobilestothekeyboardonyourPC.SecondonlytotheMotorola68HC11ineightbitprocessorssales,the89S52familyofmicrocontrollersisavailableinawidearrayofvariationsfrommanufacturerssuchasIntel,Philips,andSiemens.Thesemanufacturershaveaddednumerousfeaturesandperipheralstothe89S52suchasI2Cinterfaces,analogtodigitalconverters,watchdogtimers,andpulsewidthmodulatedoutputs.Variationsofthe89S52withclockspeedsupto40MHzandvoltagerequirementsdownto1.5voltsareavailable.Thiswiderangeofpartsbasedononecoremakesthe89S52familyanexcellentchoiceasthebasearchitectureforacompany'sentirelineofproductssinceitcanperformmanyfunctionsanddeveloperswillonlyhavetolearnthisoneplatform.Thebasicarchitectureconsistsofthefollowingfeatures:1.aneightbitALU2.32descreteI/Opins(4groupsof8)whichcanbeindividuallyaccessed3.two16bittimer/counters4.fullduplexUART5.6interruptsourceswith2prioritylevels6.128bytesofonboardRAM7.separate64KbyteaddressspacesforDATAandCODEmemoryOne89S52processorcycleconsistsoftwelveoscillatorperiods.Eachofthetwelveoscillatorperiodsisusedforaspecialfunctionbythe89S52coresuchasopcodefetchesandsamplesoftheinterruptdaisychainforpendinginterrupts.Thetimerequiredforany89S52instructioncanbecomputedbydividingtheclockfrequencyby12,invertingthatresultandmultiplyingitbythenumberofprocessorcyclesrequiredbytheinstructioninquestion.Therefore,ifyouhaveasystemwhichisusingan11.059MHzclock,youcancomputethenumberofinstructionspersecondbydividingthisvalueby12.Thisgivesaninstructionfrequencyof921583instructionspersecond.Invertingthiswillprovidetheamountoftimetakenbyeachinstructioncycle(1.085microseconds).1.MemoryOrganizationThe89S52architectureprovidestheuserwiththreephysicallydistinctmemoryspaceswhichcanbeseeninFigureA-1.Eachmemoryspaceconsistsofcontiguousaddressesfrom0tothemaximumsize,inbytes,ofthememoryspace.Addressoverlapsareresolvedbyutilizinginstructionswhichreferspecificallytoagivenaddressspace.Thethreememoryspacesfunctionasdescribedbelow.2.TheCODESpaceThefirstmemoryspaceistheCODEsegmentinwhichtheexecutableprogramresides.Thissegmentcanbeupto64K(sinceitisaddressedby16addresslines).TheprocessortreatsthissegmentasreadonlyandwillgeneratesignalsappropriatetoaccessamemorydevicesuchasanEPROM.However,thisdoesnotmeanthattheCODEsegmentmustbeimplementedusinganEPROM.ManyembeddedsystemsthesedaysareusingEEPROMwhichallowsthememorytobeoverwritteneitherbythe89S52itselforbyanexternaldevice.ThismakesupgradestotheproducteasytodosincenewsoftwarecanbedownloadedintotheEEPROMratherthanhavingtodisassembleitandinstallanewEPROM.Additionally,batterybackedSRAMcanbeusedinplaceofanEPROM.ThismethodoffersthesamecapabilitytouploadnewsoftwaretotheunitasdoesanEEPROM,anddoesnothaveanysortofread/writecyclelimitationssuchasanEEPROMhas.However,whenthebatterysupplyingtheRAMeventuallydies,sodoesthesoftwareinit.UsinganSRAMinplaceofanEPROMindevelopmentsystemsallowsforrapiddownloadingofnewcodeintothetargetsystem.Whenthiscanbedone,ithelpsavoidthecycleofprogramming/testing/erasingwithEPROM,andcanalsohelpavoidhasslesoveranincircuitemulatorwhichisusuallyararecommodity.Inadditiontoexecutablecode,itiscommonpracticewiththe89S52tostorefixedlookuptablesintheCODEsegment.Tofacilitatethis,the89S52providesinstructionswhichallowrapidaccesstotablesviathedatapointer(DPTR)ortheprogramcounterwithanoffsetintothetableoptionallyprovidedbytheaccumulator.Thismeansthatoftentimes,atable'sbaseaddresscanbeloadedinDPTRandtheelementofthetabletoaccesscanbeheldintheaccumulator.Theadditionisperformedbythe89S52duringtheexecutionoftheinstructionwhichcansavemanycyclesdependingonthesituation.Anexampleofthisisshownlaterinthischapterin.3.TheDATASpaceThesecondmemoryspaceisthe128bytesofinternalRAMonthe89S52,orthefirst128bytesofinternalRAMonthe89S52.ThissegmentistypicallyreferredtoastheDATAsegment.TheRAMlocationsinthissegmentareaccessedinoneortwocyclesdependingontheinstruction.ThisaccesstimeismuchquickerthanaccesstotheXDATAsegmentbecausememoryisaddresseddirectlyratherthanviaamemorypointersuchasDPTRwhichmustfirstbeinitialized.Therefore,frequentlyusedvariablesandtemporaryscratchvariablesareusuallyassignedtotheDATAsegment.Suchallocationmustbedonewithcare,however,duetothelimitedamountofmemoryinthissegment.VariablesstoredintheDATAsegmentcanalsobeaccessedindirectlyviaR0orR1.Theregisterbeingusedasthememorypointermustcontaintheaddressofthebytetoberetrievedoraltered.Theseinstructionscantakeoneortwoprocessorcyclesdependingonthesource/destinationdatabyte.TheDATAsegmentcontainstwosmallersegmentsofinterest.Thefirstsubsegmentconsistsofthefoursetsofregisterbankswhichcomposethefirst32bytesofRAM.The89S52canuseanyofthesefourgroupsofeightbytesasitsdefaultregisterbank.TheselectionofregisterbanksischangeableatanytimeviatheRS1andtheRS0bitsintheProcessorStatusWord(PSW).Thesetwobitscombineintoanumberfrom0to3(withRS1beingthemostsignificantbit)whichindicatestheregisterbanktobeused.Registerbankswitchingallowsnotonlyforquickparameterpassing,butalsoopensthedoorforsimplifyingtaskswitchingonthe89S52Thesecondsub-segmentintheDATAspaceisabitaddressablesegmentinwhicheachbitcanbeindividuallyaccessed.ThissegmentisreferredtoastheBDATAsegment.Thebitaddressablesegmentconsistsof16bytes(128bits)abovethefourregisterbanksinmemory.The89S52containsseveralsinglebitinstructionswhichareoftenveryusefulincontrolapplicationsandaidinreplacingexternalcombinatoriallogicwithsoftwareinthe89S52thusreducingpartscountonthetargetsystem.Itshouldbenotedthatthese16bytescanalsobeaccessedona"byte-wide"basisjustlikeanyotherbyteintheDATAspace.4.SpecialFunctionRegistersControlregistersfortheinterruptsystemandtheperipheralsonthe89S52arecontainedininternalRAMatlocations80hexandabove.Theseregistersarereferredtoasspecialfunction.Registers(orSFRforshort).Manyofthemarebitaddressable.ThebitsinthebitaddressableSFRcaneitherbeaccessedbyname,indexorbitaddress.Thus,youcanrefertotheEAbitoftheInterruptEnableSFRasEA,IE.7,or0AFH.TheSFRcontrolthingssuchasthefunctionofthetimer/counters,theUART,andtheinterruptsourcesaswellastheirpriorities.TheseregistersareaccessedbythesamesetofinstructionsasthebytesandbitsintheDATAsegment.AmemorymapoftheSFRSindicatingtheregisters.5.TheIDATASpaceCertain89S52familymemberssuchasthe89S52containanadditional128bytesofinternalRAMwhichresideatRAMlocations80hexandabove.ThissegmentofRAMistypicallyreferredtoastheIDATAsegment.BecausetheIDATAaddressesandtheSFRaddressesoverlap,addressconflictsbetweenIDATARAMandtheSFRsareresolvedbythetypeofmemoryaccessbeingperformed,sincetheIDATAsegmentcanonlybeaccessedviaindirectaddressingmodes.6.TheXDATASpace.Thefinal89S52memoryspaceis64Kinlengthandisaddressedbythesame16addresslinesastheCODEsegment.Thisspaceistypicallyreferredtoastheexternaldatamemoryspace(ortheXDATAsegmentforshort).ThissegmentusuallyconsistsofsomesortofRAM(usuallyanSRAM)andtheI/Odevicesorexternalperipheralstowhichthe89S52mustinterfaceviaitsbus.ReadorwriteoperationstothissegmenttakeaminimumoftwoprocessorcyclesandareperformedusingeitherDPTR,R0,orR1.InthecaseofDPTR,itusuallytakestwoprocessorcyclesormoretoloadthedesiredaddressinadditiontothetwocyclesrequiredtoperformthereadorwriteoperation.Similarly,loadingR0orR1willtakeminimumofonecycleinadditiontothetwocyclesimposedbythememoryaccessitself.Therefore,itiseasytoseethatatypicaloperationwiththeXDATAsegmentwill,ingeneral,takeaminimumofthreeprocessorcycles.Becauseofthis,theDATAsegmentisaveryattractiveplacetostoreanyfrequently.Itispossibletofillthissegmententirelywith64KofRAMifthe89S52doesnotneedtoperformanyI/OwithdevicesinitsbusorifthedesignerwishestocycletheRAMonandoffwhenI/Odevicesarebeingaccessedviathebus.Methodsforperformingthistechniquewillbediscussedinchapterslaterinthisbook.7.On-BoardTimer/CountersThestandard89S52hastwotimer/counters(other89S52familymembershavevaryingamounts),eachofwhichisafull16bits.Eachtimer/countercanbefunctionasafreerunningtimer(inwhichcasetheycountprocessorcycles)orcanbeusedtocountfallingedgesonthesignalappliedtotheirrespectiveI/Opin(eitherT0orT1).Whenusedasacounter,theinputsignalmusthaveafrequencyequaltoorlowerthantheinstructioncyclefrequencydividedby2(ie:theoscillatorfrequency/24)sincetheincomingsignalissampledeveryinstructioncycle,andthecounterisincrementedonlywhena1to0transitionisdetected(whichwillrequiretwosamples).Ifdesired,thetimer/counterscanforceasoftwareinterruptwhentheyoverflow.TheTCON(TimerControl)SFRisusedtostartorstopthetimersaswellasholdtheoverflowflagsofthetimers.TheTCONSFRisdetailedbelowinTableA-7.Thetimer/countersarestartedorstoppedbychangingthetimerrunbits(TR0andTR1)inTCON.ThesoftwarecanfreezetheoperationofeithertimeraswellasrestartthetimerssimplybychangingtheTrxbitintheTCONregister.TheTCONregisteralsocontainstheoverflowflagsforthetimers.Whenthetimersoverflow,theysettheirrespectiveflag(TF0orTF1)inthisregister.Whentheprocessordetectsa0to1transitionintheflag,aninterruptoccursifitisenabled.Itshouldbenotedthatthesoftwarecansetorclearthisflagatanytime.Therefore,aninterruptcanbepreventedaswellasforcedbythesoftware.8.MicrocomputerinterfaceAmicrocomputerinterfaceconvertsinformationbetweentwoforms.Outsidethemicrocomputertheinformationhandledbyanelectronicsystemexistsasaphysicalsignals,butwithintheprogram,itisrepresentednumerically.Thefunctionofanyinterfacecanbebrokendownintoanumberofoperationswhichmodifythedatainsomeway,sothantheprocessofconversionbetweentheexternalandinternalformsiscarriedoutinanumberorsteps.ThiscanbeillustratedbymeansofanexamplesuchasthanorFig10-1,whichshowsaninterfacebetweenamicrocomputerandatransducerproducingacontinuouslyvariableanalogsignal.transducersoftenproduceverysmalloutrequiringamplyfrication,ortheymaygeneratesignals.inaformthatneedstobeconvertedagainbeforebeinghandledbytherestofthesystem.Forexample,manytransducersthesevariableresistancewhichmustbeconvertedtoavoltagebyaspecialcircuit.Thisprocessofconvertingthetransduceroutputintoavoltage4signalwhichcanbeconnectedtotherestofthesystemiscalledsignalconditioning.IntheexampleofFigure10-1,thesigmaconditioningsectiontranslatestherangelfvoltageorcurrentsignalsfromthetransducertoonewhichcanbeconvertedtodigitalforumbyananalog-to-digitalconverter.TransducerADCSignalconditioningTransducerADCSignalconditioningI/OSectionI/OSectionFig10-1outputInterfaceAnalog-to-digital–digitalconverter(ADC)isusedtoconvertacontinuouslyvariablesignaltoacorrespondingdigitalforumwhichcantakeanyoneofafixednumberofpossiblebinaryvalues.Iftheoutputlfthetransducerdoesnotvarycontinuously,noADCisnecessary.Inthiscasethesignalconditioningsectionmustconverttheincomingsignaltoaformwhichcanbeconnecteddirectlytothenextpartoftheinterface,theinput/outputsectionlfthemicrocomputeritself.TheI/Osectionconvertsdigital“on/off”voltagesignalstoaformwhichcanbepresentedtotheprocessorviatheviathesystembuses.Herethestateofeachinputlinewhetheritis“on”or“off”,isindicatedbyacorresponding“1”or“0”.Inthelineinputswhichhavebeenconvertedtodigitalform,thepatternsofonesandzerosintheinternalrepresentationwillformbinarynumberscorrespondingtothequantitybeingconverted.The“raw”numbersfromtheinterfacearelimitedbythedesignoftheinterfacecircuitryandtheyoftenrequirelinearizationandscalingtoproducevaluessuitableforuseinthemainprogram.Forexample,theinterfacenightberisetoconverttemperaturesintherange–20to–+50dress,buythenumbersproducedbyan8-bitconverterwilllieintherange0to255.Obviouslyitiseasier,theprogrammer‘spointofviewtodealdirectlywithtemperatureratherthantoworkouttheequivalentofanygiventemperatureintermsofthenumbersproducedbytheADC.Everytimetheinterfaceisusedtoreadatransducer,thesameoperationsmustbecarriedouttoconverttheinputnumberintoamoreconvenientform.Addtionarly,theoperationofsomeinterfacesrequirescontrolsignalstobepassedbetweenthemicrocomputerandcomponentsoftheinterface,Forthesereasonsitisnormaltouseasubroutinetolootafterthedetailedoperationoftheinterfaceandcarryoutanyscalingand/orlinearizationwhichmightbeneeded.Outputinterfacestakeasimilarform(Fig.10-2),thebiopicdifferencebeingthatheretheflowofinformationisintheoppositedirection;itispassedfromtheprogramtotheoutsideworld.Inthiscasetheprogrammaycallanoutputsubroutinewhichsupervisestheoperationoftheinterfaceandperformsthescalingnumberswhichmaybeneededforadigital-to-analogconverter(DAC).ThissubroutinepassesinformationintermtoanoutanalogformusingaDAC.Finallythesignalisconditioned(usuallyamplified)toaformsuitableforoperatinganactuator.Fig10-2outputInterfaceThesignalsusedwithinmicrocomputercircuitsarealmostalwaystoosmalltobeconnecteddirectlytothe“outsideworld”andsomekingofinterfacemustbeusedtotranslatethemtoamoreappropriateform.Thedesignofsectionofinterfacecircuitsisoneofthemostimportanttasksfacingtheengineerwishingtoapplymicrocomputers.Wehaveseenthatinmicrocomputersinformationisrepresentedasdiscretepatternsofbits;thisdigitalformismostusefulwhenthemicrocomputeristobeconnectedtoequipmentwhichcanonlybeswitchedonoroff,whereeachbitmightrepresentthestateofaswitchoractuator.Caremustbetakenwhenconnectinglogiccircuitstoensurethattheirlogiclevelsandcurrentratingsarecompatible.Theoutputvoltagesproducedbyalogiccircuitarenormallyspecifiedintermsofworstcasevalueswhensourcingorsinkingthemaximumratedcurrents.ThusVOHistheguaranteedminimum“high”voltagewhensourcingthemaximumrate“high”outputcurrentIOH,whileVOListheguaranteed“l(fā)ow”outputvoltagewhensinkingthemaximumrated“l(fā)ow”outputcurrentIOL.Therearecorrespondingspecificationsforlogicinputswhichspecifytheminimuminputvoltagewhichwillberecognizedasalogic“high”stateVIH,andthemaximuminputvoltagewhichwillberegardedasalogic“l(fā)ow”stateVIL.Forinputinterface,perhapsthemainproblemfacingthedesigneristhatofelectricalnoise.Smallnoisesignalmaycausethesystemtomalfunction,whilelargeramountsofmoistcanpermanentlydamageit.Thedesignermustbeawareofthesedangersfromtheoutset.Therearemanymethodstoprotectinterfacecircuitsandmicrocomputerfromvariouskindsofnoise.Followingissomeexamples:1.Inputandoutputelectricalisolatingbetweenthemicrocomputersystemandexternaldevicesusinganopt-isolatororatransformer.2.Removinghighfrequencynoisepulsesbyalow-peafilterandSchmitt-trigger.3.Protectingagainstexcessiveinputvoltagesusingapairofdiodestopowersupplyreversiblybiasedinnormaldirection.Foroutputinterface,parametersVOH,VOL,IOHandIOLofalogicdeviceareusuallymuchtolowtoallowloadstobeconnecteddirectly,andinpracticeanexternalcircuitmustbeconnectedtoamplifythecurrentandvoltagetodriveaload.AlthoughseveraltypesofsemiconductordevicesarenowavailableforcontrollingDCandACpowersuptomanykilowatts,therearetwobasicwaysinwhichaswitchcanbeconnectedtoaloadtocontrolit:seriesconnectionandshuntconnectionasshowninFigure10-3.Fig10-3SeriesandShuntConnectionWithseriesconnection,theswitchallowscurrenttoflowthroughtheloadwhenclosed,whilewithshuntconnectionclosingtheswitchallowscurrenttobypasstheload.Bothconnectionsareusefulinlow-powercircuits,butonlytheseriesconnectioncanbeusedinhigh-powercircuitsbecauseofthepowerwastedintheseriesresistorR.THEINTRODUCTIONOFAT89S52FeaturesoftheAT89S52?CompatiblewithMCS-51?Products?8KBytesofIn-SystemReprogrammableFlashMemory?Endurance:1,000Write/EraseCycles?FullyStaticOperation:0Hzto24MHz?Three-levelProgramMemoryLock?256x8-BitInternalRAM?32ProgrammableI/OLines?Three16-bitTimer/Counters?EightInterruptSources?ProgrammableSerialChannel?LowPowerIdleandPowerDownModesDescriptionTheAT89S52isalow-power,high-performanceCMOS8-bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80S51and80S52instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89S52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitectureafullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAMtimer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthardwarereset.PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighby.Theinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.TABLE1--PortPinfunctionPortpinAlternateFunctionsP1.0T2(externalcountinputtoTimer/Counter2),clock-outP1.1T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)Port2Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.89S52系列微控制器89S52系列微控制器是基于高度完善的嵌入式控制系統(tǒng)的體系結(jié)構(gòu)。從軍事設(shè)備到汽車，再到PC機(jī)的鍵盤，它都有很廣泛的應(yīng)用。另外，對(duì)于摩托羅拉公司生產(chǎn)的M68HC11（8位處理器）可以應(yīng)用于不同廠商生產(chǎn)的89S52系列微控制器，如：Intel、Philips及Siemens等。這些廠商都對(duì)89S52增加了許多功能部件和外圍設(shè)備，如：12C總線接口、模/數(shù)轉(zhuǎn)換器、監(jiān)視跟蹤定時(shí)器和脈沖寬度調(diào)制輸出。89S52的允許范圍：時(shí)鐘頻率上至40MHz，電壓下至1.5V都是有效的。一個(gè)公司的生產(chǎn)線要完成許多功能，開發(fā)人員就不得不學(xué)習(xí)這個(gè)平臺(tái)，為此以89S52系列作為基本體系結(jié)構(gòu)是最好的選擇，以它為核心得到了廣泛的應(yīng)用?；倔w系結(jié)構(gòu)由下列功能部件組成：1.8位ALU；2.32個(gè)I/O引腳（4組，每組8個(gè)），可分別存?。?.2個(gè)16位定時(shí)/計(jì)數(shù)器；4.全雙工通用異步收發(fā)器；5.6個(gè)中斷源，2個(gè)中斷優(yōu)先級(jí)；6.128字節(jié)隨機(jī)存儲(chǔ)器；7.64字節(jié)地址空間，存放數(shù)據(jù)和代碼。一個(gè)89S52的處理器周期是由12個(gè)振蕩周期組成。12個(gè)振蕩周期中每一個(gè)都能完成一種特殊功能，89S52的核心如：操作碼的取出、典型的菊花鏈待定中斷。任何8051指令所需的定時(shí)都是由時(shí)鐘脈沖頻率除以12，再將所得結(jié)果乘以處理機(jī)所需的循環(huán)數(shù)計(jì)算得到。因此，如果你有一個(gè)系統(tǒng)時(shí)鐘11.059MHz，你可以用這個(gè)值除以12計(jì)算出每秒所需指令數(shù)。這里我們給出一個(gè)指令頻率921583/秒。將它轉(zhuǎn)化成實(shí)際時(shí)間，每個(gè)指令周期（1.085微妙）。1.存儲(chǔ)器組織89S52體系結(jié)構(gòu)為用戶提供了3個(gè)物理直接存儲(chǔ)空間。每個(gè)存儲(chǔ)空間占用連續(xù)地址空間，按字節(jié)從0到最大尺寸。地址重疊是通過(guò)利用引用特定地址空間指令來(lái)解決的。這三個(gè)存儲(chǔ)空間功能如下所述：2.代碼空間第一個(gè)存儲(chǔ)空間是代碼段，其中用來(lái)存放可執(zhí)行程序。這個(gè)段最大可達(dá)64K（因?yàn)樗?6根地址線）。處理機(jī)將它視為只讀，能產(chǎn)生相應(yīng)的信號(hào)對(duì)一存儲(chǔ)器件進(jìn)行存取，如可擦可編程只讀存儲(chǔ)器EPROM。然而，這不意味著代碼段必須作為EPROM的工具。目前，許多嵌入式系統(tǒng)都利用EPROM，通過(guò)89S52或一個(gè)外部設(shè)備允許對(duì)它存儲(chǔ)或改寫。這可能輕而易舉的提高產(chǎn)品，因?yàn)樾碌能浖梢韵螺d到EPROM，而不必將它分解后再安裝成一個(gè)新的EPROM。另外，電池后面的靜態(tài)存儲(chǔ)器SRAM也可用來(lái)代替EPROM。這種方法和加載軟件到電可擦可編程只讀存儲(chǔ)器EEPROM是一樣的，但是EEPROM沒有任何讀/寫周期限制。然而，當(dāng)電池電源RAM沒電了，也可如此將軟件加載到里面。在開發(fā)系統(tǒng)中若用SRAM代替EPROM，則允許在目標(biāo)系統(tǒng)中快速下載新代碼。如果可以那樣做，它將幫助我們避免對(duì)EPROM的循環(huán)執(zhí)行/測(cè)試/擦寫，同時(shí)也能幫助我們避免對(duì)通常很少使用的線路仿真器產(chǎn)生爭(zhēng)論。除可執(zhí)行程序代碼之外，89S52通常在代碼段存放安裝查找表。為了簡(jiǎn)化，89S52提供了允許快速存取查找表指令的途徑——數(shù)據(jù)指針（DPTR）或帶偏移量的程序計(jì)數(shù)器通過(guò)累加器隨意的指向查找表。通常這意味著，一個(gè)查找表的基地址能用DPTR來(lái)定位，而表中的元素可以通過(guò)累加器存儲(chǔ)。用89S52執(zhí)行加法，在指令執(zhí)行期間可以根據(jù)情況存放許多循環(huán)數(shù)。3.數(shù)據(jù)空間89S52輔助存儲(chǔ)空間是128字節(jié)的內(nèi)部RAM，而89S52的高128字節(jié)是輔助存儲(chǔ)空間。這個(gè)段被認(rèn)為是典型的數(shù)據(jù)段。RAM定位在這個(gè)段，依靠指令循環(huán)存取一次或二次。這樣存取時(shí)間比存取在XDATA段要快很多，因?yàn)榇鎯?chǔ)器直接給出地址，勝于由存儲(chǔ)指針如DPTR必須先初始化。因此，通常將已用變量和臨時(shí)定義變量都放在數(shù)據(jù)段。然而，這樣的分配會(huì)占用段中少量的存儲(chǔ)單元。數(shù)據(jù)段中的可變存儲(chǔ)器還可以由R0或R1間接存儲(chǔ)。使用寄存器作存儲(chǔ)指針就必須包含已檢索或已改變字節(jié)的地址。這些指令可以依靠源/目的數(shù)據(jù)字節(jié)使一個(gè)或二個(gè)處理機(jī)循環(huán)。數(shù)據(jù)段又包含兩個(gè)重要的小段。第一個(gè)子段由四個(gè)寄存器組組成，它占用了RAM的低32字節(jié)。89S52用這四組（每組8字節(jié)）作為缺省寄存器組。寄存器組選定區(qū)域在任何時(shí)候都通過(guò)處理機(jī)狀態(tài)字（PSW）中的RS1和RS0這兩位來(lái)改變。這兩位組合表示數(shù)0~3（RS1作最高有效位），用來(lái)指明哪個(gè)寄存器組在被使用。在89S52中，寄存器組開關(guān)不但允許快速參數(shù)傳遞，而且能打開單任務(wù)開關(guān)。在數(shù)據(jù)空間的第二個(gè)子段是一個(gè)可尋址位段，每一位都能單獨(dú)存取。這個(gè)段稱為BDATA段?？蓪ぶ返奈欢斡蓛?nèi)存中四個(gè)寄存器組16字節(jié)（128位）組成。89S52包含許多位指令，它通常用于控制某一位的應(yīng)用及在89S52中用軟件替換外部組合邏輯給予幫助，這樣在目標(biāo)系統(tǒng)中以減少部分依賴。人們注意到這個(gè)16字節(jié)還可以按“一位”寬在數(shù)據(jù)空間像其他字節(jié)一樣進(jìn)行存取。4.特殊功能寄存器89S52內(nèi)部RAM的80H以上的單元為控制寄存器，包含中斷系統(tǒng)和外部設(shè)備。這些寄存器稱為特殊功能寄存器（簡(jiǎn)稱SFR）。它們大部分是可按位尋址的。在可按位尋址的SFR中的位可以是被訪問(wèn)的名稱、索引或者是位地址。因此，你可以參看中斷允許SFR中的EA（EA、IE.7或0AFH）位。SFR可控制的東西有：定時(shí)/計(jì)數(shù)器和UART的功能。中斷源以及它們的優(yōu)先級(jí)。這些被訪問(wèn)的寄存器在數(shù)據(jù)段中的字節(jié)和位是同一張指令表。表A所示SFR的存儲(chǔ)圖中指明了可尋址的位寄存器。5.IDATA空間某些89S52家族成員，如89S52在內(nèi)部RAM中包含一個(gè)輔助128字節(jié)，存放在80H以上的單元。這個(gè)典型的RAM段被稱為IDATA段。因?yàn)镮DATA地址和SFR地址重疊，IDATARAM和SFR之間的地址沖突是通過(guò)分解被存取存儲(chǔ)器的類型來(lái)解決，因?yàn)镮DATA段只能通過(guò)間接尋址方式存取。6.XDATA空間89S52存儲(chǔ)空間為64K，代碼段可用16根地址線尋址。這個(gè)典型空間被稱為外部數(shù)據(jù)存儲(chǔ)空間（簡(jiǎn)稱XDATA段）。這個(gè)段通常由各種RAM（通常為SRAM）、I/O設(shè)備或外圍設(shè)備組成,89S52必須通過(guò)總線連接。這個(gè)段的讀或?qū)懖僮髦辽傩鑳纱窝h(huán)處理，并且它的執(zhí)行既要用到DPTR又要用到R0和R1。就DPTR來(lái)說(shuō)，它通常要在執(zhí)行讀或?qū)懖僮魉蟮膬蓚€(gè)循環(huán)外再附加加載兩個(gè)或更多循環(huán)處理地址。同樣，在一個(gè)周期內(nèi)除了利用存儲(chǔ)器自身存取之外，至少要加載R0或R1。顯而易見，XDATA段的典型操作很簡(jiǎn)單，通常最少需三個(gè)循環(huán)處理。因此，數(shù)據(jù)段常用來(lái)存儲(chǔ)常用變量。如果89S52不需要用總線執(zhí)行任何I/O設(shè)備或者設(shè)計(jì)者希望當(dāng)I/O設(shè)備通過(guò)總線存取時(shí)讓RAM循環(huán)開、關(guān)，那么它可使這個(gè)段全部占滿64KRAM。7.微機(jī)接口微機(jī)接口實(shí)現(xiàn)兩種信息形式的交換。在計(jì)算機(jī)之外，由電子系統(tǒng)所處理以一種物理形式存在，但在程序中，它是用數(shù)字表示的。任一接口的功能都可分為以某種形式進(jìn)行數(shù)據(jù)變換的一些操作，所以外部和內(nèi)部形式的轉(zhuǎn)換由許多步驟完成的。所示的情況為例加以說(shuō)明，圖中展示了微計(jì)算機(jī)和產(chǎn)生的信號(hào)和形式被系統(tǒng)的其他部分處理之前需要再次轉(zhuǎn)換.舉例來(lái)說(shuō)，許多傳感器具有電阻變化，這必須由一專門電路轉(zhuǎn)換成電壓。這種將傳感器輸出轉(zhuǎn)換成電壓信號(hào)，并與系統(tǒng)的其他電路相連接的過(guò)程，稱為信號(hào)調(diào)理。信號(hào)調(diào)理部分將源自傳感器的電壓