EDA技術與Verilog設計第六章課后習題部分答案

6-116-11試編寫求補碼的Verilog程序，輸入是帶符號的8位二進制數(shù)modulewytest(data_in,data_out);//習題6-11input[7:0]data_in;output[7:0]data_out;reg[7:0]data_out;always@(data_in)beginif(data_in[7])//正數(shù)負數(shù)判斷，從最高是否為1來判斷

data_out=((~data_in)+1)|8'h80;elsedata_out=data_in;end

endmodule6-11仿真波形8A-原碼表示的十進制數(shù)-100A----十進制數(shù)10B6-原碼表示的十進制數(shù)-5436-----十進制數(shù)5380-原碼表示的十進制數(shù)1286-126-12編寫兩個四位二進制數(shù)相減的verilog程序

modulewytest(opr1,opr2,out_data);//完成Opr1-opr2的運算

input[3:0]opr1,opr2;output[4:0]out_data;

reg[3:0]out;regcout;

function[3:0]abs;input[3:0]data;case(data[3])1'b0:abs=data;1'b1:abs=(~data)+1;//對負數(shù)求絕對值，按位取反再加1endcaseendfunction6-12always@(opr1oropr2)case({opr1[3],opr2[3]})2'b00:{cout,out}=opr1-opr2;//兩個正數(shù)相減2‘b01:{cout,out}=opr1+abs(opr2);//正數(shù)減負數(shù)，化為加法運算2‘b10:{cout,out}=-(abs(opr1)+opr2);//負數(shù)減正數(shù)，化為加法再取反2‘b11:{cout,out}=abs(opr2)-abs(opr1);//負數(shù)相減，化為絕對值相減〔順序調(diào)換〕endcase

assignout_data={cout,out};

endmodule6-126-12仿真波形6-136-13有一個比較電路，當輸入的一位BCD碼大于4時，輸出1，否那么輸出0。modulewytest(bcd_in,out);input[3:0]bcd_in;outputout;assignout=(bcd_in>4)?1:0;endmodule6-13仿真波形6-13modulewytest(bcd_in,out);//習題6-13input[3:0]bcd_in;outputout;//assignout=(bcd_in>4)?1:0;

regout;always@(bcd_in)if(bcd_in-4>0)out=1;elseout=0;endmodule6-136-14試編寫一個實現(xiàn)3輸入與非門的verilog程序；modulewytest(a,o);input[2:0]a;outputo;nandnand3(o,a[0],a[1],a[2]);endmodule6-146-156-15設計74138譯碼器電路

6-15modulewytest(s1,s2,in,out);inputs1;input[1:0]s2;input[2:0]in;output[7:0]out;reg[8:0]out;always@(s1ors2orin)beginif(s1==0)out<=8'hff;elseif((!s2[0])|(!s2[1]))out<=8'hff;elsecase(in)3'd0:out=8'b11111110;3'd1:out=8'b11111101;3'd2:out=8'b11111011;3'd3:out=8'b11110111;3'd4:out=8'b11101111;3'd5:out=8'b11011111;3'd6:out=8'b10111111;3'd7:out=8'b01111111;endcaseendendmodule

6-156-16CO=Q3Q2Q1Q0CTT注意：異步清零、同步置位6-16設計一個74161的電路。6-16modulewytest(reset,load,ctt,ctp,clk,data_in,out,co);//習題6-16inputreset,load,ctt,ctp,clk;input[3:0]data_in;output[3:0]out;outputco;reg[3:0]out;regco;always@(posedgeclkornegedgereset)

if(!reset)beginout<=4'b0;co<=1'b0;endelseif(!load)out<=data_in;elseif(!ctt)out<=out;elseif(!ctp)out<=out;elsebeginout<=out+1;if(out==14)co<=1;elseco<=0;endendmodule6-16四級流水線實現(xiàn)的32位加法器modulewytest(clk,a,b,sum,cout);input[31:0]a,b;inputclk;output[31:0]sum;outputcout;//最后輸出的結果reg[31:0]sum;regcout;//第一級流水線的輸出reg[7:0]fist_sum;regfirst_cout;//第一級流水線要緩存的數(shù)據(jù)//未用的數(shù)據(jù)緩存reg[7:0]first_a_31_24,first_a_23_16,first_a_15_8;reg[7:0]first_b_31_24,first_b_23_16,first_b_15_8;

四級流水線實現(xiàn)的32位加法器//第二級流水線的輸出reg[7:0]second_sum;regsecond_cout;//第二級流水線要緩存的數(shù)據(jù)//未用的數(shù)據(jù)緩存reg[7:0]second_a_31_24,second_a_23_16;reg[7:0]second_b_31_24,second_b_23_16;//第一級流水線計算結果緩存reg[7:0]first_sum_1;//第一級流水線計算結果第一次緩存//第三級流水線輸出reg[7:0]third_sum;regthird_cout;//第三級流水線要緩存的數(shù)據(jù)//未用的數(shù)據(jù)緩存reg[7:0]third_a_31_24;reg[7:0]third_b_31_24;//第一級、第二級流水線計算結果緩存reg[7:0]first_sum_2;//第一級流水線計算結果第二次緩存；reg[7:0]second_sum_1;//第二級流水線計算結果第一次緩存；四級流水線實現(xiàn)的32位加法器//第一級流水線always@(posedgeclk)begin{first_cout,fist_sum}<=a[7:0]+b[7:0]+cout;first_a_31_24<=a[31:24];first_b_31_24<=b[31:24];first_a_23_16<=a[23:16];first_b_23_16<=b[23:16];first_a_15_8<=a[15:8];first_b_15_8<=b[15:8];end//第二級流水線always@(posedgeclk)begin{second_cout,second_sum}<=first_a_15_8+first_b_15_8+first_cout;second_a_31_24<=first_a_31_24;second_b_31_24<=first_b_31_24;second_a_23_16<=first_a_23_16;second_b_23_16<=first_b_23_16;first_sum_1<=fist_sum;

end四級流水線實現(xiàn)的32位加法器//第三級流水線always@(posedgeclk)begin{third_cout,third_sum}<=second_a_23_16+second_b_23_16+second_cout;third_a_31_24<=second_a_31_24;third_b_31_24<=second_b_31_24;

first_sum_2<=first_sum_1;second_sum_1<=second_sum;end//第四級流水線always@(posedgeclk)begin{cout,sum[31:24]}<=third_a_31_24+third_b_31_24+third_cout;

sum[23:0]<={third_sum,second_sum_1,first_sum_2};endendmodule四級流水線實現(xiàn)的32位加法器8x8乘法器實現(xiàn)modulewytest(out,a,b,clk);input[7:0]a,b;inputclk;output[15:0]out;reg[15:0]out;reg[3:0]firsta,firstb;reg[3:0]seconda,secondb;wire[7:0]outa,outb,outc,outd;always@(posedgeclk)beginfirsta[3:0]<=a[7:4];seconda[3:0]<=a[3:0];firstb[3:0]<=b[7:4];secondb[3:0]<=b[3:0];endmul4x4m1(outa,firsta,firstb,clk),m2(outb,seconda,firstb,clk),m3(outc,firsta,secondb,clk),m4(outd,seconda,secondb,clk);always@(posedgeclk)out<=(outa<<8)+(outb<<4)+(outc<<4)+outd;

endmodule8x8乘法器實現(xiàn)用另一種方法實現(xiàn)：將8位數(shù)字分成4段，每段兩位，那么操作數(shù)可表示如下：

A=A1X26+A2X24+A3X22+A4B=B1X26+B2X24+B3X22+B4

AXB=(A1X26+A2X24+A3X22+A4)X(B1X26+B2X24+B3X22+B4)

上式展開后，要做16次2X2的乘法，調(diào)用16次lookup函數(shù)然后再做移位相加的處理。

7-5編寫4位并-串轉換電路modulewytest(clk,rst,in,out);inputclk,rst;input[3:0]in;outputout;regout;reg[1:0]i;always@(posedgeclk)beginif(rst)begini<=2'd0;out<=1'd0;endelseif(i<=3)beginout<=in[i];i<=i+1;endend模為9的占空比50%的奇數(shù)分頻modulewytest(RESET,CLK,COUT);inputCLK,RESET;outputCOUT;reg[3:0]m,n;wireCOUT;regCOUT1,COUT2;assignCOUT=COUT1|COUT2;always@(posedgeCLK)beginif(!RESET)beginCOUT1<=0;//輸出信號初態(tài)為0m<=0;//計數(shù)初值為0endelseif(RESET)

begin

if(m==8)//n-1beginm<=0;endelsem<=m+1; if(m==3)//N/2-1.5COUT1=~COUT1;elseif(m==7)//N-2COUT1=~COUT1;endendalways@(negedgeCLK)beginif(!RESET)beginCOUT2<=0;n<=0;endelseif(RESET)begin if(n==8) begin n<=0; end else n<=n+1; if(n==3) COUT2=~COUT2; elseif(n==7) COUT2=~COUT2;endendEndmodule模為9的占空比50%的奇數(shù)分頻模為9.3的小數(shù)分頻分頻方法：9分頻7次，10分頻3次modulefdiv8_1(clk_in,rst,clk_out);inputclk_in,rst;outputclk_out;regclk_out;reg[3:0]cnt1; //cnt1計8分頻的次數(shù)reg[3:0]cnt2;//cnt2為兩個分頻器的計數(shù)值always@(posedgeclk_inorposedgerst)beginif(rst)begincnt1<=0;cnt2<=0;clk_out<=0; endelseif(cnt1<7) //9分頻7次

beginif(cnt2<8)//9分頻的前8個脈沖的處理

begincnt2<=cnt2+1;clk_out<=0;endelse//處理最后一個輸入脈沖

begincnt2<=0;clk_out<=1;cnt1<=cnt1+1;end end模為9.3的小數(shù)分頻elseif(cnt1<10)begin if(cnt2<9)//10分頻的前9個脈沖處理begincnt2<=cnt2+1;clk_out<=0;end elsebegincnt2<=0;clk_out<=1;if〔cnt1==9〕cnt1<=0;els