VHDL電子時鐘的設計.doc

現(xiàn)代電子系統(tǒng)設計中北學院現(xiàn)代電子系統(tǒng)設計_數(shù)字電子鐘實驗報告姓名:葉子班級:0932班學號:專業(yè):電子信息工程任課教師:倪小琦完成時間:2012年5月19日2518093203葉子目錄第一章數(shù)字電子鐘功能簡介3第二章數(shù)字電子鐘原理介紹32.1數(shù)字電子鐘基本原理 32.2數(shù)字電子鐘電路組成 3第三章利用QuartusII設計數(shù)字電子鐘 73.1按鍵去抖動模塊 73.2分頻電路模塊 93.3選擇器模塊133.4計數(shù)模塊143.5分位電路模塊183.6數(shù)碼管動態(tài)顯示掃描模塊213.7數(shù)碼管動態(tài)顯示模塊22第四章仿真與實現(xiàn)25第一章數(shù)字電子鐘功能簡介 計時功能：這是本計時器設計的基本功能，可進行時、分、秒計時，并顯示在6個七段數(shù)碼管上。 調(diào)時功能：當需要校時，可通過實驗箱上的按鍵控制，按下對應的按鍵，可調(diào)整對應的時、分狀態(tài)。第二章數(shù)字電子鐘原理簡介2.1數(shù)字電子鐘基本原理 數(shù)字鐘電路的基本結(jié)構(gòu)由兩個60進制計數(shù)器和一個24進制計數(shù)器組成，分別對秒、分、小時進行計時，當計時到23時59分59秒時，再來一個計數(shù)脈沖，計數(shù)器清零，重新開始計時。秒計數(shù)器的計數(shù)時鐘CLK為1Hz的標準信號，可以由27MHz信號通過分頻得到。當數(shù)字鐘處于計時狀態(tài)時，秒計數(shù)器的進位輸出信號作為分鐘計數(shù)器的計數(shù)信號，分鐘計數(shù)器的進位輸出信號又作為小時計數(shù)器的計數(shù)信號。時、分、秒的計時結(jié)果通過6個數(shù)碼管來動態(tài)顯示。數(shù)字鐘除了能夠正常計時外，還應能夠?qū)r間進行調(diào)整。可通過模式選擇信號控制數(shù)字鐘的工作狀態(tài)，即控制數(shù)字鐘，使其分別工作于正常計時，調(diào)整分、時和設定分、時狀態(tài)。當數(shù)字鐘處于計時狀態(tài)時，3個計數(shù)器允許計數(shù)，且秒、分、時計數(shù)器的計數(shù)時鐘信號分別為CLK，秒的進位, 分的進位；當數(shù)字鐘處于調(diào)整時間狀態(tài)時，被調(diào)的分或時會一秒一秒地增加。2.2數(shù)字電子鐘電路組成 本實驗數(shù)字電子鐘的設計電路主要由七個模塊組成，分別是：按鍵去抖動模塊、分頻電路模塊、選擇器模塊、計數(shù)模塊、分位電路模塊、數(shù)碼管動態(tài)顯示掃描模塊、數(shù)碼管動態(tài)顯示模塊。按鍵去抖動模塊如圖2-1所示 圖2-1分頻電路模塊如圖2-2所示圖2-2選擇器模塊如圖2-3所示圖2-3計數(shù)模塊如圖2-4所示圖2-4分位電路模塊如圖2-5所示圖2-5數(shù)碼管動態(tài)顯示掃描模塊如圖2-6所示圖2-6數(shù)碼管動態(tài)顯示模塊如圖2-7所示圖2-7電路圖整體設計如圖2-8所示圖2-8第三章利用QuartusII設計數(shù)字電子鐘3.1按鍵去抖動模塊按鍵去抖動模塊的元件設計如圖3-1所示圖3-1按鍵去抖動的VHDL語言設計如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity debounce isport(clk:in std_logic;qcin:in std_logic;qcout:out std_logic);end debounce;architecture behave of bounce istype state is (S0,S1,S2);signal current: state;Beginprocess(clk,qin)begin if(clkevent and clk = 1) thencase current iswhen S0 = qcout = 1;if(qcin = 0) thencurrent = S1;elsecurrent qcout = 1;if(qcin = 0) thencurrent = S2;elsecurrent qcout = 0;if(qcin = 0) thencurrent = S2;elsecurrent qcout = 1;current = S0;end case;end if;end process;end behave;/3.2分頻電路模塊分頻電路模塊元件設計如圖3-2所示：圖3-2分頻模塊VHDL語言設計如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk1kHz isgeneric(N: integer:=50000); port(clk: in std_logic;clk1kHz: out std_logic);end clk1kHz;architecture behave of clk1kHz issignal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk1KHz = temp;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk1Hz isgeneric(N: integer:=50000000); port(clk: in std_logic;clk1Hz: out std_logic);end clk1Hz;architecture behave of clk1Hz is signal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk1Hz = temp;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk10Hz isgeneric(N: integer:=20000000); port(clk: in std_logic;clk10Hz: out std_logic);end clk10Hz;architecture behave of clk10Hz issignal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk10Hz = temp;end behave;/3.3選擇器模塊選擇器模塊元件設計如圖3-3所示：圖3-3選擇器模塊VHDL與顏色合計如下所示：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xzq isport(sel: in std_logic;date0,date1:in std_logic;dcout:out std_logic);end xzq;architecture behave of xzqisbeginwith sel selectdcout =date0 when 0, date1 when others;end behave;/3.4計數(shù)模塊計數(shù)模塊元件設計如圖3-4所示：圖3-4計數(shù)器模塊VHDL語言設計如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60s isport(clk:in std_logic;clk10:in std_logic;set: in std_logic:=1;change: out std_logic;qcout: buffer integer range 0 to 59:=0);end count60s;architecture behave of count60s issignal temp:integer range 0 to 59;signal temp1:std_logic; begin process(clk,set,clk10) begin if(set=0) thentemp = 0; elsif(clkevent and clk=1) then if(qcout=59) thentemp = 0;temp1 = 1; elsetemp = temp+1;temp1 = 0; end if; end if; qcout = temp; change = temp1; end process; end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60m isport(clk:in std_logic;change: out std_logic;qcout: buffer integer range 0 to 59:=0;set:in std_logic:=1);end count60m;architecture behave of count60m issignal temp:integer range 0 to 59;signal temp1:std_logic; begin process(clk) begin if(clkevent and clk=1) then if(qcout=59) thentemp = 0;temp1 = 1; elsetemp = temp+1;temp1 = 0; end if; end if; qcout = temp; if(set = 1)thenchange = car;end if; end process; end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count24h isport(clk:in std_logic;qcout: buffer integer range 0 to 23:=0);end count24h;architecture behave of count24h issignal temp:integer range 0 to 23; begin process(clk) begin if(clkevent and clk=1)then if(qcout=23) thentemp = 0; elsetemp = temp+1; end if; end if; qcout = temp; end process; end behave;/3.5分位電路模塊分位電路模塊元件設計如圖3-5所示圖3-5分位電路模塊VHDL語言設計如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit isport(cnt: in integer range 0 to 59;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit;architecture behave of decircuit isbegin-fenwei circuitprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit isport(cnt: in integer range 0 to 59;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit;architecture behave of decircuit isbeginprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit2 isport(cnt: in integer range 0 to 23;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit2;architecture behave of decircuit2 isbegin-fenwei circuitprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/3.6數(shù)碼管動態(tài)顯示掃描模塊圖3-6元件設計如圖3-6所示：圖3-6數(shù)碼管動態(tài)顯示掃描模塊VHDL語言設計如下：library ieee;use ieee.std_logic_1164.al