EDA實(shí)驗(yàn)1-6.doc

實(shí)驗(yàn)一：五人表決器方案1-編程：library ieee;use ieee.std_logic_1164.all;entity vote5 isport(a,b,c,d,e:in std_logic; f:out std_logic);end;architecture vo of vote5 isbeginf=(a and b and c) or (a and b and d) or (a and b and e) or (a and c and d) or (a and c and e) or (a and d and e) or (b and c and d) or (b and c and e) or (b and d and e) or (c and d and e); end;方案2-作圖：實(shí)驗(yàn)二一位全加器一、布爾方程實(shí)現(xiàn)全加器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder ISPORT (a,b,ci:IN STD_LOGIC; S, co:OUT STD_LOGIC);END fulladder; -以下是一位全加器結(jié)構(gòu)體數(shù)據(jù)流描述ARCHITECTURE Dataflow OF fulladder ISBEGINS = a XOR b XOR ci;co = (a AND b) OR (b AND ci) OR (a AND ci);END Dataflow;二、with select when實(shí)現(xiàn)全加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder ISPORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC);END fulladder;ARCHITECTURE behavioral OF fulladder ISSIGNAL inputsingal:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL outputsingal:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINinputsingal=a&b&ci;WITH inputsingal SELECToutputsingal = 00 WHEN 000,10 WHEN 001,10 WHEN 010,01 WHEN 011,10 WHEN 100,01 WHEN 101,01 WHEN 110,11 WHEN 111,00 WHEN OTHERS;s=outputsingal(1);co=outputsingal(0); END behavioral;三、when else實(shí)現(xiàn)全加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY fulladder ISPORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC);END fulladder;ARCHITECTURE behavioral OF fulladder ISBEGIN s = 1 WHEN (a= 0 AND b= 1 AND ci= 0) ELSE 1 WHEN (a= 1 AND b= 0 AND ci= 0) ELSE 1 WHEN (a= 0 AND b= 0 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 1 AND ci= 1) ELSE 0; co = 1 WHEN (a= 1 AND b= 1 AND ci= 0) ELSE 1 WHEN (a= 0 AND b= 1 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 0 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 1 AND ci= 1) ELSE 0;END behavioral;四、if then else實(shí)現(xiàn)全加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder ISPORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC);END fulladder;ARCHITECTURE behavioral OF fulladder ISBEGINp1:PROCESS(a, b, ci)BEGINIF(a= 0 AND b= 0 AND ci= 0) THEN s = 0;co = 0; ELSIF(a= 0 AND b= 0 AND ci= 1) THEN s = 1;co = 0; ELSIF(a= 0 AND b= 1 AND ci= 0) THEN s = 1;co = 0;ELSIF(a= 0 AND b= 1 AND ci= 1) THEN s = 0;co = 1; ELSIF(a= 1 AND b= 0 AND ci= 0) THEN s = 1;co = 0;ELSIF(a= 1 AND b= 0 AND ci= 1) THEN s = 0;co = 1;ELSIF(a= 1 AND b= 1 AND ci= 0) THEN s = 0;co = 1;ELSIF(a= 1 AND b= 1 AND ci= 1) THEN s = 1;co = 1; Elses = 0;co = 0;END IF;END PROCESS p1; END behavioral;五、case when實(shí)現(xiàn)全加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder ISPORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC);END fulladder;ARCHITECTURE behavioral OF fulladder ISSIGNAL inps:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL outs:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINinps outs outs outs outs outs outs outs outs outs=00;END CASE;s=outs(0);co=outs(1);END PROCESS p1;END behavioral;實(shí)驗(yàn)三四位全加器第一種方法：頂層文件為原理圖第二種方法library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity add4 isport(a3,a2,a1,a0,b3,b2,b1,b0:in std_logic; f:out std_logic_vector(4 downto 0);end;architecture add of add4 isbeginprocess(a3,a2,a1,a0,b3,b2,b1,b0)variable c,d:std_logic_vector(4 downto 0):=00000;beginc:=(0,a3,a2,a1,a0);d:=(0,b3,b2,b1,b0);f=c+d;end process;end;實(shí)驗(yàn)四 16進(jìn)制數(shù)碼顯示library ieee;use ieee.std_logic_1164.all;entity tran isport(a:in std_logic_vector(3 downto 0); s:out std_logic_vector(2 downto 0); f:out std_logic_vector(6 downto 0);end;architecture tt of tran isbeginprocess(a)begins f f f f f f f f f f f f f f f f = 1110001; -f end case;end process;end;實(shí)驗(yàn)六 交通燈LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY traffic isGENERIC( green1:integer:=25;-定義主道綠燈亮25S yellow1 :integer:=5 ;-定義主道黃燈亮5S green2:integer:=25;-定義支道綠燈亮15S yellow2 :integer:=5);-定義支道黃燈亮5SPORT( CLK,RST: IN STD_LOGIC; lgt1_r,lgt1_y,lgt1_g,lgt2_r,lgt2_y,lgt2_g: out STD_LOGIC);End traffic;ARCHITECTURE rtl of traffic isType states is (st0,st1,st2,st3);-定義控制器各種狀態(tài)Signal state:states:=st0; -初始化狀態(tài)Signal cnt:integer range 0 to 30:=1;-定義計(jì)數(shù)器Signal cnt_enb:std_logic:=0; -初始化計(jì)數(shù)器使能信號(hào)beginProcess(clk,rst)Begin if (rst=1) then state=st0; cnt=1;Elsif (clkevent and clk=1) then if (cnt_enb=1) then cnt=cnt+1;-計(jì)數(shù)器計(jì)數(shù) else cnt if (cnt=green1 ) then state=st1;Elsestate if (cnt=yellow1 ) then state=st2;Elsestate if (cnt=green2 ) then state=st3;Elsestate if (cnt=yellow2 ) then state=st0;Elsestate lgt1_r=0; lgt1_y=0; lgt1_g=1; lgt2_r=1; lgt2_y=0; lgt2_g=0; Cnt_enb=1; if (cnt=green1) then cnt_enb lgt1_r=0; lgt1_y=1; lgt1_g=0; lgt2_r=1; lgt2_y=0; lgt2_g=0; Cnt_enb=1; if (cnt=yellow1) then cnt_enb lgt1_r=1; lgt1_y=0; lgt1_g=0; lgt2_r=0; lgt2_y=0; lgt2_g=1; Cnt_enb=1; if (cnt=green2) then cnt_enb lgt1_r=1; lgt1_y=0; lgt1_g=0; lgt2_r=0; lgt2_y=1; lgt2_g=0; Cnt_enb=1; if (cnt=yellow2) then cnt_enb=0; end if;End case;End process;end rtl;實(shí)驗(yàn)六 60進(jìn)制計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity con60 isport(clk3,clk5,rst,en:in std_logic; seg_sel:out std_logic_vector(2 downto 0); seg_da:out std_logic_vector(7 downto 0); co:out std_logic);end;architecture cc of con60 is COMPONENT CNT10 PORT(CLK,rst,cin:IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT :OUT STD_LOGIC); END COMPONENT; COMPONENT CNT6 PORT(CLK,rst,cin :IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC); END COMPONENT;SIGNAL SEG_BUF1,SEG_BUF2:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SEG_CNT :STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL SEG_TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL COUT:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL CLK:STD_LOGIC; BEGIN PROCESS (CLK3) BEGIN IF CLK3EVENT AND CLK3=1 THEN CLK=NOT CLK ; END IF; END PROCESS; PROCESS (CLK) BEGIN IF CLKEVENT AND CLK=1 THEN IF seg_cnt=001 THEN SEG_CNT=000; ELSE SEG_CNT=SEG_CNT+1; END IF; END IF; END PROCESS; SEG_SEL SEG_TEMP SEG_TEMP NULL; END CASE; END PROCESS; PROCESS (SEG_TEMP) BEGIN CASE SEG_TEMP IS WHEN 0000 = SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA SEG_DA=x6F; END CASE; END PROCESS; U1 : CNT10 PORT MAP (CLK5,RST,1,SEG_BUF1,COUT(0); U2 : CNT6 PORT MAP (CLK5,RST,COUT(0),SEG_BUF2,co); END ; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;ENTITY CNT10 IS PORT(CLK :IN STD_LOGIC; RST :IN STD_LOGIC; CIN :IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC );END CNT10;ARCHITECTURE BEHAVE OF CNT10 ISSIGNAL CNT_T:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF RST=1 THEN CNT_T=0000; ELSIF CLKEVENT AND CLK=1 THEN IF CIN=1 THEN IF CNT_T/= 9 THEN CNT_T=CNT_T+1; ELSE CNT_T=00