華南理工大學(xué) 2013年_數(shù)字系統(tǒng)設(shè)計(jì)(全英)試題 B卷

1、誠信應(yīng)考誠信應(yīng)考,考試作弊將帶來嚴(yán)重后果！考試作弊將帶來嚴(yán)重后果！ 華南理工大學(xué)期末考試華南理工大學(xué)期末考試 數(shù)字系統(tǒng)設(shè)計(jì)（全英課）數(shù)字系統(tǒng)設(shè)計(jì)（全英課） 試卷試卷 B B （2014.1.162014.1.16） 注意事項(xiàng)：注意事項(xiàng)：1.1. 考前請將密封線內(nèi)各項(xiàng)信息填寫清楚；考前請將密封線內(nèi)各項(xiàng)信息填寫清楚； 2.2. 所有答案請?jiān)谠嚲砩洗痤}；所有答案請?jiān)谠嚲砩洗痤}； 3 3考試形式：閉卷；考試形式：閉卷； 4.4. 本試卷共本試卷共 三三 大題，滿分大題，滿分 100100 分，分，考試時(shí)間考試時(shí)間 120120 分鐘分鐘。 題題 號號一一二二三三總分總分 得得 分分 評卷人評卷人 1.

2、 Multiple choice test（210=20 marks） 1. Which of the following VHDL data types can be used directly， without explicit declaration? （ C ） A. STD_LOGIC ；B. STD_LOGIC_VECTOR；C. BIT；D. ARRAY 2. Which of the following statements on sequential circuit is true（ B ） A. In synchronous circuit, the actions of

3、Flip-Flops are not necessarily synchronized by the same clock signal B. In asynchronous circuit, the states of Flip-Flops dont change simultaneously C. The input change of Moore state machine is directly reflected by output 3. Which of the following statements on PLD is not true （ B ） A. Spartan is

4、the product of Altera B. FPGA is based on product terms C. FPGA is field programmable gate array 4. Which of the following statements is concurrent ?（ D ） A. loop statement B.CASE statement C. wait statement D.WHENELSEstatement 5. Which of the following statements on VHDL description of ASM chart is

5、 not true ( C ) AIn one-process description style, output can be synchronized BTwo-process description style can avoid unwanted registers CTwo-process description style consumes more resources than one-process description 6. Which of the following circuits is sequential? （C ） A. Priority Encoder B.

6、3-8 decoder C. Flip-Flop _ _ 姓名 學(xué)號 學(xué)院 專業(yè) 座位號 ( 密 封 線 內(nèi) 不 答 題 ) 密封線 線 D. XOR gate 7. Which of the following VHDL statements can be used for the description inside the process? ( A ) A. sequential statements B. both sequential and concurrent statements C. concurrent statementsD. any VHDL statement is

7、ok. 8. For state encoding in state machine, which of the following scheme is more simple for decoding at the prices of more Flip-Flops in encoding: ( A ) A. one hot code B. Natural binary code C.Gray code 9. Which of the following statements on VHDL is true? （ B ） A. For a VHDL design, entity is not

8、 unique B. For a VHDL design, architecture is not unique C. For a VHDL design, the circuit after synthesis is unique. 10. Which one is not the basic element of ASM chart? （ D ） A. State box B. conditional output box C. decision box D. transition box 2. Short answer questions（ 54=20 marks） 1Please gi

9、ve a brief introduction to the concept of EDA EDA: electronic design automation. In contrast to traditional design which is bottom-up, EDA is top-down design concept. 2Please give a brief introduction to sequential logic circuit, and its classification in terms of output signals Sequential logic cir

10、cuit : The outputs of a system depend on past values of its inputs as well as the present state values.(depend on both present state and history state) It can be classified into synchronous sequential circuit and asynchronous sequential circuit. 3Please clarify the difference between VHDL signal and

11、 VHDL variable, from the perspective of assignment, declaration, and synthesis. Signal is an abstraction of wire in hardware, for connection between components Variable has no corresponding hardware, just for high level computation, or temporal data storage Signal is global, for multiple processes V

12、ariable is local, valid in its process only Signal assignment has delay, while variable assignment takes effect immediately. Signal can carry history information, while variable has current value only. 4. Please specify the difference between inertial delay and transport delay. Inertial delay models

13、 only propagate signals to an output after the input signals have remained unchanged (been stable) for a time period equal to or greater than the propagation delay of the model. If the time between two input changes is shorter than a procedural assignment delay, a continuous assignment delay, or gat

14、e delay, a previously scheduled but unrealized output event is replaced with a newly scheduled output event. Transport delay models propagate all signals to an output after any input signals change. Scheduled output value changes are queued for transport delay models. 3. Comprehension ENTITY MUX IS

15、PORT(oe, a, b, sel: in std_logic; y: out std_logic); END MUX; ARCHITECTURE BEHAV OF MUX IS BEGIN PROCESS(oe,a,b,sel) BEGIN If oe=1 then if sel=0 then y=a; else y=b; end if; else y=Z; end if; END PROCESS: END ARCHITECTURE; 2、Please describe the following RTL diagram using VHDL including VHDL entity a

16、nd VHDL architecture. （10 marks） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF2 IS PORT(CLK, A1: IN STD_LOGIC; Z:OUT STD_LOGIC); END; ARCHITECTURE bhv OF DFF2 IS SIGNAL B:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK =1 THEN B=A1; Z=B; END IF; END PROCESS; END bhv; 3、Please give a

17、VHDL design for a 2-4 decoder, according to the following table. (Both VHDL entity and VHDL architecture are required) （10 marks） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY 24DECO IS PORT(G, B, A: IN STD_LOGIC; Y0,Y1,Y2,Y3: OUT STD_LOGIC); END; ARCHITECTURE BHV OF 24DECO IS SIGNAL SEL:STD_LOG

18、IC_VECTOR(1 DOWNTO 0); SIGNAL TMP: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN SEL TMP TMP TMP TMP TMP=“ZZZZ”; END CASE; ELSE TMP=“0000” END IF; END PROCESS; Y0=TMP(0); Y1=TMP(1); Y2=TMP(2); Y3=TMP(3); END ARCHITECTURE; 4、As a part of testbench, please describe the following signals （6 marks） Signal S1：std_

19、logic; Signal S2：std_logic; Process Begin S1=0; Wait for 10 ns; S1=1; Wait for 5 ns; S1=0; Wait for 10 ns; End process; Process Begin S1=0; Wait for 5 ns; S1=1; Wait for 15 ns; S1=0; Wait for 5 ns; End process; 5、Please complete the VHDL design for a D-Flip-Flop with strobe signal (片選信號片選信號)and asyn

20、chronous reset signal. (Both VHDL entity and VHDL architecture are required) （7 marks） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF IS PORT(CLK, RESET, CS, D: IN STD_LOGIC; QS: OUT STD_LOGIC); END; ARCHITECTURE BHV OF DFF IS BEGIN PROCESS(CLK, RESET) BEGIN IF (RESET = 1) THEN Q = 0; ELSIF R

21、ISING_EDGE(CLK) THEN IF (CS_SELECT = 1) THEN Q = D; END IF; END IF; END PROCESS; END ARCHITECTURE; 6. Please read each piece of the following codes carefully. Does each of them have the same circuit behavior like the following circuit diagram? If no, please give the reasons.（9 marks） （a） process beg

22、in wait until rising_edge(clk); d = not c; c = a and b; end process; (b) process begin wait until rising_edge(clk); c1 = a and b; c2 = not c1; d = c2; end process; (c) process begin wait until rising_edge(clk); c1 = a and b; d = c2; end process; process (c1) begin c2 = not c1; end process; (a) yes: (b) no: extra register is introduced. (c) yes 7、Design a serial data transmitter (串行數(shù)據(jù)發(fā)送器串行數(shù)據(jù)發(fā)送器)。 Parallel data input Z of 8 bits is loaded firstly in the transmitter, and