xx大學(xué)計(jì)算機(jī)原理實(shí)驗(yàn)四多周期MIPSCPU存儲(chǔ)器實(shí)驗(yàn)預(yù)習(xí)報(bào)告

1、湘潭大學(xué)計(jì)算機(jī)原理 實(shí)驗(yàn)四 多周期MIPS CPU + 存儲(chǔ)器實(shí)驗(yàn)預(yù)習(xí)報(bào)告實(shí)驗(yàn)四 多周期MIPS CPU +存儲(chǔ)器實(shí)驗(yàn)1、深入理解Ml PS- CPU指令系統(tǒng)的功能和工作原理;掌握多周期CPU的工作原理和邏輯功能實(shí)現(xiàn);3、熟練掌握用 Verilog HDL 語(yǔ)言設(shè)計(jì)多周期存儲(chǔ)器的方法;4、熟練掌握對(duì)多周期存儲(chǔ)器的仿真實(shí)驗(yàn)驗(yàn)證和硬件測(cè)試兩種調(diào)試方法；5、通過(guò)對(duì)多周期CPU的運(yùn)行情況進(jìn)行觀 察和分析，進(jìn)一步加深理解。硬件：現(xiàn)代計(jì)算機(jī)組成原理實(shí)驗(yàn)系統(tǒng)Nios 32位嵌入式系統(tǒng)實(shí)驗(yàn)開(kāi)發(fā)平臺(tái) EP1C12Q240Corei3-3240 CPU 的內(nèi)存 軟件：QuartusIIMicrosoft Wind

2、ows xp1、設(shè)計(jì)一個(gè)32位Ml PS多周期CPU 口休的要求如下:至少運(yùn)行下列的6類(lèi)32條Ml PS指令。算術(shù)邏輯指令and、 sub、 addi邏輯運(yùn)算指令and、Or、xor、 andi 、 ori 、 xori 位移指令 sll、srl、sra 條件分支指令beq、bne、無(wú)條件跳轉(zhuǎn)指令j、jr數(shù)據(jù)傳送指令lw、sw 2.設(shè)計(jì)一個(gè)存儲(chǔ)器四. 實(shí)驗(yàn)原理與步驟實(shí)現(xiàn)上述原理框圖根據(jù)功能將其分劃分為控制單元(cunit)、執(zhí)行單元(eunit)、指令單元(iunit)以及存儲(chǔ)單元(munit)四大模塊。.控制單元(cunit)是多周期微處理器的核心控制微處理器取指令、指令譯碼和指令執(zhí)行等工作

3、。主要指令譯碼(ALU器控制器(outputs control)、算術(shù)邏輯運(yùn)算控制器control)兩 個(gè)子模塊組成。.執(zhí)行單元(eunit)主要寄存器堆(registers) 和算術(shù)邏輯單元(ALU)兩個(gè)子模塊組成。其中寄存器是微處理器最基 本的元素 MIPS系統(tǒng)的寄存器堆32個(gè)32位寄存器組成而ALU則是微處理器的主要功能部件 執(zhí)行加，減，比較等算術(shù)運(yùn)算和與、或、或非、異或等邏輯運(yùn)算。指令單元(iunit) 的作用是決定下一條指令的地址PC值O.存儲(chǔ)單元(munit)存儲(chǔ)器(memory)、指令寄存器(instruction register)和存儲(chǔ)數(shù)據(jù)寄存器(memory datareg

4、ister) 組成。五. 實(shí)驗(yàn)源代碼 寄存器元件代碼:module regfile (ma,mb,d,wn,we,clk,clm,qa,qb);input 4:0rna,rnb,wn;input 31:0 d; inputwe,clk,clrn;out put31:0qa,qb; reg 31:0register 1:31;assignqa = (rna = 0) 0 :registerrna;assignqb = (rnb = 0)0 :registerrnb;always (po sedge clk or negedge clrn) begin if(clrn = 0) begininte

5、ger i;for (i=1; ia4:0;endcase4b1111:cal=$signed(b)a4:0;endfunction endmodule其他部件:module f (reg_dest,jal,wn);input4:0reg_dest; inputjal; out pu t 4:0 wn; assignwn = reg_dest | 5jal; endmodulemodule sa (di,dot); input4:0 di; out put31:0outdot; assign dot = 27b0,di; endmodulemodule out4 (out); out put3

6、1:0 out; assign=32h4; endmoduleinputmodule e (immin,sext,immediate,offset);15:0 immin;inputsext;out put31:0immediate,offset; wiree = sext & immin15;wire 15:0 imm = 16e; assign offset =assignimm13:0,immin15:0,1b0,1b0;immediate = imm,immin15:0; endmodulemodule xxbine (address,pc,add);input25:0address;

7、 input 3:0pc;out put31:0add;assign addp c3:0,address25:0,1b0,1b0;endmodulemoduleconvert1input(dain,sain,o p, func,rs,rt,rd,imm,addr);output31:0 dain; out put 4:0 sain,rs,rt,rd;5:0 op ,func; out put 15:0 imm; out put 25:0 addr; assign sain = dain10:6; assign op = dain31:26; assign func = dain5:0; ass

8、ign rs = dain25:21; assign rt = dain20:16;assignrddain15:11;assignimmdain15:0;assignaddrdain25:0;endmoduleinput 31:0 pc;module convert2 (pc,pcout);out pu t 3:0 p cout; assign p cout = p c31:28;endmodule存儲(chǔ)器內(nèi)的測(cè)試數(shù)據(jù):-Co pyright (C) 1991-20XX Altera Corporation -Your use of Altera Corpo rations design to

9、ols,logic functions - and other software and tools, andits AMPP p artner logic - functions, and any out put files from any of the foregoing - (including devicep rogrammingor simulation files), and any associated documentation or information are exp ressly subject - to the terms and conditions of the

10、 AlteraProgram LicenseSubscri ptionAgreement, AlteraAgreement, or otherMegaCore Function License app licable license agreement, including, - without limitation, that your use is for the sole purp ose ofp rogramming logic devices manufactured byAltera and sold byAltera or its authorizeddistributors.P

11、 lease refer to theapp licableagreement for further details.Quartus IIgenerated MemoryInitializationFile(.mif)DEPTH= 64;%Memorydepth and width arerequiredWIDTH32;%Enter a decimalnumberADDRESS RADIXHEX; -dress and value radixes areOCT; unlessoptional DATA_RADIX = HEX; %Enter BIN, DEC, HEX, or%otherwi

12、se sp ecified, radixes = HEXCONTENT BEGIN0.3F : 00000000; % Range-Every address from 0to 3F = 00000000 0 : 3c010000; % (00) main: lui r1,0 # address of data0 1: 34240080; %(04) ori r4,r1,0x80# address of data0 2 : 20XX0004; % (08)addi r5, r0, 4 # counter3 : 0c000018; %(0c)call:swjal sum # call funct

13、ion 4: ac820XX0; %(10)r2, 0(r4) # store result 5 : 8c890000; % (14) Iwr9, 0(r4) # check sw 6: 01244022; % (18)subr8,r8,r9, r4 # sub: r8 16 = ffff8000(arith) r8, r8, 15# 15 = 0001ffff(logic) finish # dead loopr0, r0 # sumr9, 0(r4) # load datar4, 4address + 4r8, r8, r9 # sumr5, -1 # counter1r5,r0,loop

14、 # finishr2, r8, 0 # move resultto v0 r31# return% % % % % % % %六. EDA階段的實(shí)驗(yàn)結(jié)果仿真結(jié)果如上圖。七. 測(cè)試時(shí)的電路總體結(jié)構(gòu)及其說(shuō)明 實(shí)驗(yàn)電路圖八. 測(cè)試計(jì)劃及其相關(guān)說(shuō)明 輸出說(shuō)明:且將顯示高四位，pc對(duì)應(yīng)pc31.O 且將顯示低兩位，alu對(duì)應(yīng)alu31.O且將顯示低兩位clock輸入clockmem_clk pc 輸出aluir輸入mem_clk pc 輸出aluir于引腳及輸出需要，故下表ir對(duì)應(yīng)ir31.O九. 關(guān)于實(shí)驗(yàn)電路設(shè)計(jì)的其他說(shuō)明于引腳及輸出需要，故只輸出ir、pc、aluir31.O切將顯示ir高四位，p

15、c31.O低兩位，alu31.O 低兩位,q、adr、fromm、a、b、tom將不會(huì)輸出.前期實(shí)驗(yàn)總結(jié)本次實(shí)驗(yàn)，不僅加深了我對(duì)多周期CPU及存儲(chǔ)器相關(guān)知識(shí)的理解，而且?guī)椭约夯貞浐蛷?fù)習(xí)了單周期CPU方面的知識(shí)，比如如何用 Verilog HDL描述ALU模塊、一些數(shù)據(jù)選擇器、符號(hào)擴(kuò)展電路、以及寄存器。實(shí)驗(yàn)四 多周期MIPS CPU +存儲(chǔ)器實(shí)驗(yàn)1、深入理解Ml PS- CPU指令系統(tǒng)的功能和工作原理;掌握多周期CPU的工作原理和邏輯功能實(shí)現(xiàn);3、熟練掌握用 Verilog HDL 語(yǔ)言設(shè)計(jì)多周期存儲(chǔ)器的方法;4、熟練掌握對(duì)多周期存儲(chǔ)器的仿真實(shí)驗(yàn)驗(yàn)證和硬件測(cè)試兩種調(diào)試方法；5、通過(guò)對(duì)多周期CP

16、U的運(yùn)行情況進(jìn)行觀察和分析，進(jìn)一步加深理解。硬件：現(xiàn)代計(jì)算機(jī)組成原理實(shí)驗(yàn)系統(tǒng)Nios 32位嵌入式系統(tǒng)實(shí)驗(yàn)開(kāi)發(fā)平臺(tái) EP1C12Q240Corei3-3240 CPU 的內(nèi)存 軟件：QuartusIIMicrosoft Windows xp1、設(shè)計(jì)一個(gè)32位Ml PS多周期CPU 具體的耍求如下:至少運(yùn)行下列的6類(lèi)32條MIPS指令。算術(shù)邏輯指令and、 sub、 addi邏輯運(yùn)算指令and、 Or、 xor、 andi 、 ori 、 xori 位移指令sll、srl、sra條件分支指令beq、bne、無(wú)條件跳轉(zhuǎn)指令j、jr數(shù)據(jù)傳送指令lw、sw 2.設(shè)計(jì)一個(gè)存儲(chǔ)器四.實(shí)驗(yàn)原理與步驟實(shí)現(xiàn)上述

17、原理框圖根據(jù)功能將其分劃分為控制單元(cunit)、執(zhí)行單元(eunit)、指令單元(iunit)以及存儲(chǔ)單元(munit)四大模塊。.控制單元(cunit)是多周期微處理器的核心控制微處理器取指令、指令譯碼和指令執(zhí)行等工作。主要指令譯碼(ALU器控制器(outputs control)、算術(shù)邏輯運(yùn)算控制器control)兩 個(gè)子模塊組成。.執(zhí)行單元(eunit)主要寄存器堆(registers) 和算術(shù)邏輯單元(ALU)兩個(gè)子模塊組成。其中寄存器是微處理器最基本的元素MIPS系統(tǒng)的寄存器堆32個(gè)32位寄存器組成而ALU則是微處理器 的主要功能部件 執(zhí)行加、減.比較等算術(shù)運(yùn)算和與、或、或非、異

18、或等邏輯運(yùn)算。指令單元(iunit)的作用是決定下一條指令的地址PC值O.存儲(chǔ)單元(munit)存儲(chǔ)器(memory)、指令寄存器(instruction register)和存儲(chǔ)數(shù)據(jù)寄存器(memory dataregister) 組成。五.實(shí)驗(yàn)源代碼 寄存器元件代碼:module regfile (ma,mb,d,wn,we,clk,clm,qa,qb);input 4:0rna,rnb,wn;input 31:0 d; inputwe,clk,clrn;out put31:0qa,qb; reg 31:0register 1:31;assignqa = (rna = 0) 0 :regi

19、sterrna;assignqb = (rnb = 0)0 :registerrnb;always (po sedge clk or negedge clrn) begin if(clrn = 0) begininteger i;for (i=1; i32;i=i+1)registeri = 0; end else beginif(wn != 0) & (we = 1)registerwn = d; endend endmodule32位四選一選擇器:a0,a1,a2,a3;module mux4x32 (a0,a1,a2,a3,s,y); in put 31:0input 1:0 s;out

20、 put31:0 y;function 31:0 select; inp ut 31:0 a0,a1,a2,a3;input 1:0 s; case (s)2b00:select=a0;2b01: select = a1;2b10: select = a2;2b11:select = a3; endcase endfunctionassignselect (a0,a1,a2,a3,s); endmodule/r1-r31 /read /read/reset/write5位二選一選擇器:module mux2x5 (a0,a1,s,y);input4:0a0,a1;input s; out pu

21、 t4:0 y; assign y = s a1 : a0;endmodulea0,a1;32位二選一選擇器:module mux2x32 (a0,a1,s,y); in put 31:0input s; out put31:0 y; assign y=s a1 : a0;endmodule存儲(chǔ)器元件:module mcmen(clk,dataout, datain, addr, we, inclk,outclk); in put 31:0 datain; in put 31:0 addr;input clk, we, inclk, outclk; out put31:0 dataout;wi

22、re write_enable = we & clk; Ipm _ram_dq ram(.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamwidth=32; defparam _widthad = 6;defparamindata= defparam _outdata = defparamfile= defparam _address_controlendmodule控制部件:module mccu(op, func, z, clock,

23、 resetn, wpc, wir,wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca,alusrcb,pcsource, jal, sext, state); input 5:0op,func; input z, clock, resetn; out put reg wpc,wir, wmem,wreg, iord, regrt, m2reg; out putreg3:0aluc; out putreg 1:0 alusrcb,p csource; out putregreg2:0 next_state;p arameter2:0sif

24、=3b000,/IF statesid = 3b001,/ IDstatesexe = 3b010,/ EXE statesmem =3b011,state/ MEM stateswb = 3b100;/ WBwireshift, alusrca, jal, sext; out put reg 2:0 state;r_typ e,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,ijr;wirei_addi,i_andi,i_on,i_xon,i_lw,i_sw,i_beq,i_bne,i lui,i_j,i_jal;and(r_ty pe,o p5

25、,o p 4,o p3,o p 2,o p1,o p0 )；and(i_add,r_t ype,func5,func4,func3,func2,func1,func0)；and(i_sub,r_t ype,func5,func4,func3,func2,and(i_and,r_t ype,func1,func0);func5,func4,func3,func2,func1,func0);and(i_or,r_type,func5,func4,func3,func2,func1,func0);and(i_xor,r_t ype,func5,func4,func3,func2,func1,func

26、0);and(i_sll,r_t yp e,func5,func4,func3,func2，func1,func0);and(i_srl,r_t yp e,func5,func4,func3,func2,func1,func0);an d(i_sra,r_t yp e,f un c5,f un c4,fu nc3,f un c2,func1,funcO);and(i_jr,r_typ e,f un c5,f un c4,func3,func2,func1,func0);an d(i_addi, op 5, op 4,op 3,o p2,o p1,o p 0);an d(i_a ndi,op 5, o