[畢業(yè)設(shè)計精品] 應(yīng)用VHDL引用LPM庫設(shè)計32位加法器

1、 課程名稱 eda 學(xué) 院 電 信 專 業(yè) 電 信 班 級 三 班 學(xué) 號 姓 名 指導(dǎo)老師 目錄第一章、 題目.3第二章、 設(shè)計步驟.4第三章、 設(shè)計心得.40第四章、 參考文獻(xiàn).41第一章 題目應(yīng)用vhdl引用lpm庫設(shè)計32位加法器。要求在quartus ii軟件，利用vhdl完成層次式電路設(shè)計，電路中的元件可以用vhdl設(shè)計也可以用庫元件連線構(gòu)成再封裝。借助eda工具中的綜合器，適配器，時序仿真器和編程器等工具進(jìn)行相應(yīng)處理。輸入方法不限制。適配元件不限制。要求綜合出rtl電路，并進(jìn)行仿真輸入波形設(shè)計并分析電路輸出波形。第二章 設(shè)計步驟新建工程輸入設(shè)計項目并存盤：利用lpm_add_su

2、b函數(shù)。參數(shù)設(shè)定：引腳分配：程序清單：options name_substitution = on;include addcore;include look_add;include bypassff;include altshift;include alt_stratix_add_sub;include alt_mercury_add_sub;parameters (lpm_width,lpm_representation = signed,lpm_direction = default,- controlled by add_sub portone_input_is_constant = n

3、o,lpm_pipeline = 0,maximize_speed = 5,registered_at_end = 0,optimize_for_speed = 5,use_cs_buffers = 1,carry_chain = ignore,carry_chain_length = 32,device_family,use_wys = off,style = normal,cbxi_parameter = nothing);include aglobal90.inc;% device family definitions %function cbxi_parameter (aclr, ad

4、d_sub, cin, clken, clock, dataalpm_width-1.0, datablpm_width-1.returns (cout, overflow, resultlpm_width-1.0);- a useful macrodefine min(a, b) = a lpm_width) ? (latency - lpm_width) : 0;constant reg_last_adder = (latency = lpm_width) # (registered_at_end = 1) ? 1 : 0;define ovflow_extra_depth() = (lp

5、m_representation = signed # lpm_representation = unsigned & used(add_sub) ? reg_last_adder :- partial adders (for pipelined cases)constant rwidth = lpm_width mod int_latency;- # of adders on the right sideconstant lwidth = int_latency - rwidth;- # of adders on the left sideconstant sub_width1 = floo

6、r(lpm_width div int_latency);- width of right-side addersconstant sub_width0 = sub_width1 + 1;- width of left-side adders- =- look-ahead adder section- =- number of 8-bit adder blocks in carry-look-ahead casesconstant look_ahead_block_size = 8;constant blocks = ceil(lpm_width div look_ahead_block_si

7、ze);- will use the look-ahead adder?constant use_look_ahead = -(!(lpm_width look_ahead_block_size) #(family_flex() = 1) & (use_carry_chains() # (!use_carry_chains() & speed_max_factor = (!(family_flex() = 1) & (style = normal & speed_max_factor 1 generate- carry-in nodecin_node : node;cout_node: nod

8、e;unreg_cout_node : node;- datab nodesif (family_flex() = 1) generateif (use_carry_chains() generateif used(add_sub) & one_input_is_constant = no generatedatab_nodelpm_width-1.0 : lcell; else generatedatab_nodelpm_width-1.0 : node; end generate;else generateif used(add_sub) & one_input_is_constant =

9、 no generatedatab_nodelpm_width-1.0 : soft; else generatedatab_nodelpm_width-1.0 : node; end generate;end generate;else generateif used(add_sub) & one_input_is_constant = no generatedatab_nodelpm_width-1.0 : soft; else generatedatab_nodelpm_width-1.0 : soft; end generate;end generate;if (lpm_represe

10、ntation = unsigned & lpm_direction != sub) & used(add_sub) generateadd_sub_ffint_latency-2.0: bypassff with (width = 1);end generate;- cases where pipeline structure is needed -if !(family_flex() = 1) generate- non-flex cases- if a nonhomogenous adder, generate the longer (right side) adders if rwid

11、th 0 generate adder0rwidth-1.0 : addcore with (width = sub_width0,direction = add,use_cs_buffers = use_cs_buffers);datab0_ffint_latency-1.0rwidth-1.0: bypassff with (width = sub_width0);end generate;- generate the shorter (left side) addersadder1lwidth-1.0: addcore with (width = sub_width1, directio

12、n = add,use_cs_buffers = use_cs_buffers);datab1_ffint_latency-1.0lwidth-1.0 : bypassff with (width = sub_width1);- dataa pipeline registers dataa_ffint_latency-2.0: bypassff with (width = lpm_width);else generate- flex cases- if a nonhomogenous adder, generate the longer (right side) adders if rwidt

13、h 0 generateadder0rwidth-1.0 : addcore with (width = sub_width0 + 1,direction = add,use_cs_buffers = use_cs_buffers);if rwidth 1 generateadder0_0rwidth-1.1 : addcore with (width = sub_width0 + 1,direction = add,use_cs_buffers = use_cs_buffers);end generate;adder1lwidth-1.0: addcore with (width = sub

14、_width1 + 1,direction = add,use_cs_buffers = use_cs_buffers);adder1_0lwidth-1.0: addcore with (width = sub_width1 + 1,direction = add,use_cs_buffers = use_cs_buffers);datab0_ffint_latency-1.0rwidth-1.0: bypassff with (width = sub_width0+1);else generateadder1lwidth-1.0: addcore with (width = sub_wid

15、th1 + 1,direction = add,use_cs_buffers = use_cs_buffers);if lwidth 1 generateadder1_0lwidth-1.1: addcore with (width = sub_width1 + 1,direction = add,use_cs_buffers = use_cs_buffers);end generate; end generate;datab1_ffint_latency-1.0lwidth-1.0 : bypassff with (width = sub_width1+1);if lpm_represent

16、ation = signed generatesign_ffint_latency-2.0: bypassff with (width = 2);end generate;end generate; else generate- non-pipelined adder cases- will use a look-ahead type adder for flex/normal with speed_max_factor 5 or- max/fast cases. will use a ripple type adder for all other cases. if used(clock)

17、# (use_look_ahead = 0) generateadder : addcore with (width = lpm_width, direction = lpm_direction, representation = lpm_representation, use_cs_buffers = use_cs_buffers);cout_node : node;oflow_node : node;else generate cin_node : node; cout_node : node; oflow_node : node;datab_nodelpm_width-1.0 : sof

18、t; adderblocks-1.0 : addcore with (width = 8,direction = default,use_cs_buffers = use_cs_buffers);look_ahead_unit : look_add with (width = blocks);end generate; end generate; result_nodelpm_width-1.0 : node;result_ext_latency_ffs: altshift with (width = lpm_width, depth = ext_latency);carry_ext_late

19、ncy_ffs: altshift with (width = 1, depth = ext_latency);oflow_ext_latency_ffs: altshift with (width = 1, depth = ext_latency);end generate; - stratixend generate; -mercuryend generate; - stratixiibeginassert report lpm_width = % lpm_width severity debug;assert report latency = % latency severity deb

20、ug;assert report lwidth = % lwidth severity debug;assert report rwidth = % rwidth severity debug;assert report int_latency = % int_latency severity debug;assert report ext_latency = % ext_latency severity debug;assert report sub_width1 = % sub_width1 severity debug;assert (lpm_representation = signe

21、d # lpm_representation = unsigned)report illegal value for lpm_representation parameter (%) - value must be signedlpm_representationseverity errorhelp_id lpm_add_sub_representation;assert (lpm_width 0)report lpm_width parameter value must be greater than 0severity errorhelp_id lpm_add_sub_width;asse

22、rt (used(clock) ? latency 0 : latency = 0)report value of lpm_pipeline parameter must be greater than 0 if clock input is used andseverity errorhelp_id lpm_add_sub_clock_without_latency;assert (latency 0)report value of lpm_width parameter must be greater than 0severity errorhelp_id lpm_add_sub_widt

23、h2;assert (lpm_representation = unsigned # lpm_representation = signed)report illegal value for lpm_representation parameter (%) - value must be unsigned (thelpm_representationseverity errorhelp_id lpm_add_sub_representation2;assert (one_input_is_constant = yes # one_input_is_constant = no)report il

24、legal value for one_input_is_constant parameter (%) - value must be yes or no one_input_is_constantseverity errorhelp_id lpm_add_sub_iconstant;assert (lpm_direction = default # lpm_direction = add # lpm_direction = sub)report illegal value for lpm_direction parameter (%) - value must be add, sub, or

25、 defaulpm_directionseverity errorhelp_id lpm_add_sub_direction;assert (lpm_direction = default # used(add_sub) = 0)report value of lpm_direction parameter (%) is not consistent with the use of the add_sulpm_directionseverity errorhelp_id lpm_add_sub_direction_add_sub;- the next assertion is not impl

26、emented because max+plus ii implementation - differs from the lpm standard. both overflow and cout are allowed - in max+plus ii.-assert (used(overflow) = 0 # used(cout) = 0)-report cant use overflow port if cout port is used-severity error-help_id lpm_add_sub_overcout;assert (family_is_known() = 1)r

27、eport megafunction lpm_add_sub does not recognize the current device family (%) - ensure tdevice_familyseverity warninghelp_id lpm_add_sub_family_unknown;if cbx_family() = 1 & cbxi_parameter != nothing generateif used(aclr) generateauto_generated.aclr = aclr;end generate;if used(add_sub) generateaut

28、o_generated.add_sub = add_sub;end generate;if used(cin) generateauto_generated.cin = cin;end generate;if used(clken) generateauto_generated.clken = clken;end generate;if used(clock) generateauto_generated.clock = clock;end generate;if used(cout) generatecout = auto_generated.cout;end generate;if use

29、d(dataa) generateauto_generated.dataa = dataa;end generate;if used(datab) generateauto_generated.datab = datab;end generate;if used(overflow) generateoverflow = auto_generated.overflow;end generate;if used(result) generateresult = auto_generated.result;end generate;else generate- mercury wysiwyg add

30、erif family_mercury() = 1 & use_wys = on generateresult = mercury_adder.result;if used (cout) generatecout = mercury_adder.cout;end generate;if used(overflow) generateoverflow = mercury_adder.overflow;end generate;mercury_adder.dataa = dataa;mercury_adder.datab = datab;if used(cin) generatemercury_a

31、dder.cin = cin;end generate;if used(clock) generatemercury_adder.clock = clock;end generate;if used(aclr) generatemercury_adder.aclr = aclr;end generate;if used(clken) generatemercury_adder.clken = clken;end generate;if used(add_sub) generatemercury_adder.add_sub = add_sub;end generate;else generate

32、- stratix wysisyg adderif family_stratix() = 1 & (use_wys = on # used(add_sub) & (use_carry_chains() generateresult = stratix_adder.result;if used(cout) generatecout = stratix_adder.cout;end generate;if used(overflow) generateoverflow = stratix_adder.overflow;end generate;stratix_adder.dataa = dataa

33、;stratix_adder.datab = datab;if used(cin) generatestratix_adder.cin = cin;end generate;if used(clock) generatestratix_adder.clock = clock;end generate;if used(aclr) generatestratix_adder.aclr = aclr;end generate;if used(clken) generatestratix_adder.clken = clken;end generate;if used(add_sub) generat

34、estratix_adder.add_sub = add_sub;end generate;else generate- default addcore adderif int_latency 1 generateif used(cin) generatecin_node = cin;else generateif lpm_direction = sub generatecin_node = vcc;else generatecin_node = !add_sub; end generate;end generate;if (lpm_representation = unsigned & lp

35、m_direction != sub) & used(add_sub) generateadd_sub_ff0.d0 = add_sub;if int_latency 2 generateadd_sub_ffint_latency-2.1.d0 = add_sub_ffint_latency-3.0.q0;end generate;add_sub_ff.(clk, clrn, ena) = (clock, !aclr, clken);end generate;if lpm_direction = sub generatedatab_node = !datab;else generateif u

36、sed(add_sub) generatedatab_node = datab $ !add_sub;else generatedatab_node = datab;end generate;end generate;if !(family_flex() = 1) generate- non-flex cases- clock connections - adders clock/aclr/clken/add_sub connections if rwidth 0 generateadder0rwidth-1.0.(clock, aclr, clken) = (clock, aclr, clk

37、en);if (lwidth 1) generateadder1lwidth-2.0.(clock, aclr, clken) = (clock, aclr, clken);end generate;else generate if lwidth 1 generateadder1lwidth-2.0.(clock, aclr, clken) = (clock, aclr, clken);end generate;end generate;if reg_last_adder = 1 generateadder1lwidth-1.(clock, aclr, clken) = (clock, acl

38、r, clken);end generate;dataa_ff.(clk, clrn, ena) = (clock, !aclr, clken);if rwidth 0 generateif rwidth 1 generatedatab0_ff0rwidth-1.1.(clk, clrn, ena) = (clock, !aclr, clken);end generate;datab1_ff0lwidth-1.0.(clk, clrn, ena) = (clock, !aclr, clken);else generatedatab1_ff0lwidth-1.1.(clk, clrn, ena) = (clock, !aclr, clken);end generate;-carry_ffint_lat