北郵數(shù)電實(shí)驗(yàn)VHDL源代碼完整2013年

1、北郵數(shù)電實(shí)驗(yàn)VHDL源代碼完整版注：北郵信通院數(shù)電實(shí)驗(yàn)，大二下共四次實(shí)驗(yàn)，以下為四次實(shí)驗(yàn)的完整代碼，僅供參考，希望學(xué)弟學(xué)妹在抄代碼的時(shí)候了解每一行代碼的含義。知識是自己的。別忘了，北郵的未來靠你們。注意事項(xiàng)：1學(xué)校部分電腦打不開07版word文件（后綴docx），建議大家準(zhǔn)備一份TXT以防萬一2運(yùn)行出錯(cuò)時(shí)可能是你輸入有誤，比如中文和英文符號弄錯(cuò)了3數(shù)電實(shí)驗(yàn)很簡單，但要心細(xì)，一定要按老師說的做4數(shù)電實(shí)驗(yàn)報(bào)告千萬不要抄襲，老師判斷力很強(qiáng)實(shí)驗(yàn)一：半加器老師會給出，全加器是畫圖，怎么畫書上有，不用源代碼。實(shí)驗(yàn)二：（1）3位二進(jìn)制數(shù)比較器LIBRARY IEEE;USE IEEE.STD_LOGIC_1

2、164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY comp3 IS PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC);END comp3;ARCHITECTURE behave OF comp3 ISBEGIN PROCESS(A,B) BEGIN IF(AB)THEN YA=1;YB=0;YC=0; ELSIF(AB)THEN YA=0;YB=1;YC=0; ELSE YA=0;YB=0;YC Y=D0

3、;YB Y=D1;YB Y=D2;YB Y=D3;YB Y=Z;YB=Z; END CASE; END PROCESS;END behave;（3）8421碼轉(zhuǎn)換為格雷碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY trans1 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END trans1;ARCHITECTURE trans_gray OF trans1 ISBEGI

4、NB(0)=A(0)XOR A(1);B(1)=A(1)XOR A(2); B(2)=A(2)XOR A(3);B(3) B B B B B B B B B B B=ZZZZ;END CASE;END PROCESS;END trans_ex3;（5）數(shù)碼管譯碼器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sunyu_encoder ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(6 DOWNTO

5、0); C:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END sunyu_encoder;ARCHITECTURE encoder_arch OF sunyu_encoder ISBEGINPROCESS(A)BEGINC B B B B B B B B B B B=ZZZZZZZ;END CASE;END PROCESS;END encoder_arch;實(shí)驗(yàn)三：注：以下的AAA（1）（2）（3）（4）為課前做好的，但課上老師要求有了些變化，實(shí)際上機(jī)的代碼在下面BBB中AAA（1）帶異步復(fù)位的四位二進(jìn)制減計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOG

6、IC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_1 ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_1;ARCHITECTURE a OF count_1 ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset=0 THENq_temp =1111;ELSIF clkEVENT AND clk=1 THENq_temp =

7、q_temp-1;END IF;END PROCESS;q= q_temp;END a;（2）帶異步復(fù)位的8421碼十進(jìn)制計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWN

8、TO 0);BEGINPROCESS(clk,reset)BEGINIF reset=0 THENq_temp =0000;ELSIF clkEVENT AND clk=1 THENIF q_temp=1001 THENq_temp =0000;ELSE q_temp =q_temp+1;END IF;END IF;END PROCESS;q= q_temp;END a;（3）分頻器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div_12 ISPORT(clk:IN STD_LO

9、GIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12;ARCHITECTURE a OF div_12 ISSIGNAL temp:INTEGER RANGE 0 TO 11;BEGINp1:PROCESS(clear,clk)BEGINIF clear=0THENtemp=0;ELSIF clkEVENT AND clk=1 THENIF temp=11 THENtemp=0;ELSE temp=temp+1;END IF;END IF;END PROCESS p1;p2:PROCESS(temp)BEGINIF temp6 THE

10、Nclk_out=0;ELSE clk_out=1;END IF;END PROCESS p2;END a;（4）帶異步復(fù)位的四位環(huán)形計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(

11、3 DOWNTO 0);BEGINPROCESS(clk,reset) -0001-0010-0100-1000-0001BEGINIF reset=0 THEN nextcount nextcount nextcount nextcount nextcount=0001;END CASE;END IF;END PROCESS;countout=nextcount;END behave;BBBLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,r

12、eset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset=1 THENq_temp =0000;ELSIF clkEVENT AND clk=1 THENIF q_temp=1001 THENq_temp =0000;ELSE q_temp =q_temp+1;END IF;END IF;END PRO

13、CESS;q= q_temp;END a;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;-clk_out:out STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL temp:ST

14、D_LOGIC;BEGINp1:PROCESS(clk)VARIABLE count:integer range 0 to 25000000;BEGINIF( clkEVENT AND clk=1 )THENIF (count=25000000) THENcount:=0;temp=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS p1;-clk_out=temp;p2:PROCESS(temp,reset) -0001-0010-0100-1000-0001BEGINIF reset=1 THEN nextcount nextcou

15、nt nextcount nextcount nextcount=0001;END CASE;END IF;END PROCESS p2;countout=nextcount;END behave;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div_12new ISPORT(clk:IN STD_LOGIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12new;ARCHITECTURE a OF div_12new ISS

16、IGNAL temp:STD_LOGIC;BEGINPROCESS(clear,clk)VARIABLE count:integer range 0 to 5;BEGINif (clear=1) thencount:=0;ELSIF( clkEVENT AND clk=1 )THENIF (count=5) THENcount:=0;temp=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS;clk_out=temp;END a;實(shí)驗(yàn)四：這個(gè)稍有難度，而且書上沒有多少參考代碼，仔細(xì)研究哦（1）數(shù)碼管顯示012345library ie

17、ee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity nixietube1 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end nixietube1;architecture a of nixietube1 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_ve

18、ctor(5 downto 0);signal tempclk: std_logic;signal count: integer range 0 to 50000;beginp1:process(clk)beginif(clkevent and clk=1)thenif count=50000 thencount=0;tempclk= not tempclk;elsecount cat=011111;part cat=101111;part cat=110111;part cat=111011;part cat=111101;part cat=111110;part cat=011111;pa

19、rt=1111110; -0end case;end if;end process p2;catout=cat;partout=part;end a;（2）數(shù)碼管滾動(dòng)顯示012345library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shiyan12new2 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiya

20、n12new2;architecture a of shiyan12new2 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signal number: std_logic_vector(5 downto 0);signal tempclk: std_logic;-a clk(div 1)signal move: std_logic;-a clk(div 2)beginp1:process(clk)-div 1 (cat 0-5)variable count:intege

21、r range 0 to 50000:=0;beginif(clkevent and clk=1)thenif(count=50000)thencount:=0;tempclkcatcatcatcatcatcat=011111;end case;end if;end process p2;catout=cat;p3:process(clk)-div 2 (one cat and change) about 1Hzvariable count:integer range 0 to 25000000:=0;beginif (clkevent and clk=1) thenif (count=250

22、00000) thencount:=0;movenumbernumbernumbernumbernumbernumbernumbernumbernumbernumbernumbernumberpartpartpartpartpartpartpart=1111110;end case;end process p5;partout=part;end a;（3）數(shù)碼管滾動(dòng)顯示012345，且用全滅的數(shù)碼管填充右邊，直至全滅library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shiyan12ne

23、w3 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiyan12new3;architecture a of shiyan12new3 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signal number: std_logic_vector(5 downto 0);signal tempclk: std_logic;-a clk(d