數(shù)學(xué)Verilog數(shù)字系統(tǒng)設(shè)計(jì)PPT課件

1、第1頁(yè)/共57頁(yè)與C語(yǔ)言的比較第2頁(yè)/共57頁(yè)Hierarchical DesignTop LevelModuleSub-Module1Sub-Module2Basic Module3Basic Module2Basic Module1Full AdderHalf AdderHalf AdderE.g.第3頁(yè)/共57頁(yè)Modulein1in2inNout1out2outMmy_modulemodule my_module(out1, ., inN);output out1, ., outM;input in1, ., inN;. / declarations. / description of

2、 f (maybe. / sequential)endmodule第4頁(yè)/共57頁(yè)由關(guān)鍵詞：Moduleendmodule定義第5頁(yè)/共57頁(yè)模塊結(jié)構(gòu)例1：D觸發(fā)器module dff_pos (data, clk, q)input data,clk;output q;reg q;always (posedge clk) q = data;endmoduleCase sensitivitymyid Myid第6頁(yè)/共57頁(yè)模塊引用module top (D, CLK, Q)input D, CLK;Output Q;reg Q;dff_pos DFF1(.data(D),.clk(CLK),

3、.q(Q)dff_pos DFF2(.data(D),.endmodule第7頁(yè)/共57頁(yè)Example: Half Addermodule half_adder(S, C, A, B);output S, C;input A, B;wire S, C, A, B;assign S = A B;assign C = A & B;endmoduleHalfAdder第8頁(yè)/共57頁(yè)Example: Full Addermodule full_adder(sum, cout, in1, in2, cin);output sum, cout;input in1, in2, cin;wire

4、sum, cout, in1, in2, cin;wire I1, I2, I3;half_adder ha1(I1, I2, in1, in2);half_adder ha2(sum, I3, I1, cin);assign cout = I2 | I3;endmoduleInstancenameModulenameHalfAdder ha2HalfAdder 1ha1in1in2cincoutsumI1I2I3第9頁(yè)/共57頁(yè)Hierarchical Namesha2.ARemember to use instance names,not module namesHalfAdder ha2

5、HalfAdder 1ha1in1in2cincoutsumI1I2I3第10頁(yè)/共57頁(yè)wire signed PhaseWidth+5:0 SignPhaseError;reg signed PhaseWidth+5:0 SignPhaseError_d;assign SignPhaseError = in_Dir?(-in_PE) : in_PE ;always (posedge in_UpdateClk) begin if (in_ResetFilter) SignPhaseError_d = 0; else SignPhaseError_d = SignPhaseError; end

6、 連續(xù)賦值語(yǔ)句、過(guò)程塊、實(shí)例引用三項(xiàng)是順序執(zhí)行，但是always內(nèi)的語(yǔ)句是順序執(zhí)行的。第11頁(yè)/共57頁(yè)基本詞法基本詞法 命名 注釋 邏輯狀態(tài) 數(shù)字第12頁(yè)/共57頁(yè)數(shù)據(jù)命名規(guī)則 從以下符號(hào)中任意組合A-Z, a-z, 0-9, _, $, 但是不能以 $ 或者 0-9數(shù)字開(kāi)頭 myidentifier m_y_identifier 3my_identifier $my_identifier _myidentifier$ Case sensitivity myid Myid第13頁(yè)/共57頁(yè)注釋行與C語(yǔ)言完全一致 / The rest of the line is a comment /* M

7、ultiple line comment*/ /* Nesting /* comments */ do NOT work */第14頁(yè)/共57頁(yè)四種邏輯狀態(tài)0represents low logic level or false condition1represents high logic level or true conditionxrepresents unknown logic level（不定態(tài)）zrepresents high impedance logic level（高阻態(tài)）第15頁(yè)/共57頁(yè)數(shù)字(i) 8h ax = 1010 xxxx 12o 3zx7 = 011zzzx

8、xx111No of bitsBinary b or BOctal o or ODecimal d or DHexadecimal h or HConsecutive chars 0-f, x, z第16頁(yè)/共57頁(yè)數(shù)字(ii) 可以插入“_”符號(hào)便于閱讀 12b 000_111_010_100 12b 000111010100 12o 07_24 Bit extension MS bit = 0, x or z extend this 4b x1 = 4b xx_x1 MS bit = 1 zero extension 4b 1x = 4b 00_1xRepresent the same n

9、umber第17頁(yè)/共57頁(yè)數(shù)字 (iii) 如果 size（位寬）沒(méi)標(biāo)出，默認(rèn)值是32位，每個(gè)字母用8位ASII碼值表示 如果 radix（進(jìn)制）沒(méi)標(biāo)出，默認(rèn)為十進(jìn)制 15 = d 15第18頁(yè)/共57頁(yè)數(shù)據(jù)類型數(shù)據(jù)類型1.是對(duì)硬件電路中的信號(hào)連線和寄存器等物理量的描述，而不是一般一般計(jì)算機(jī)語(yǔ)言的整型、實(shí)型等2.Verilog中兩種數(shù)據(jù)類型：線型wire和寄存器型reg，區(qū)別在于： 驅(qū)動(dòng)方式（賦值方式） 保持方式 硬件實(shí)現(xiàn)第19頁(yè)/共57頁(yè)第20頁(yè)/共57頁(yè)第21頁(yè)/共57頁(yè)線型數(shù)據(jù)類型nets (i) 用于連接器件原件，相當(dāng)于版圖中的金屬走線 當(dāng)某個(gè)節(jié)點(diǎn)沒(méi)有任何連接時(shí)，等效為高阻態(tài) net

10、s數(shù)據(jù)類型 wire wand(wired-AND) wor(wired-OR) tri(tri-state) 下面的例子中：只要A或者B發(fā)生變化，Y的值就會(huì)持續(xù)的自動(dòng)更新第22頁(yè)/共57頁(yè)線型數(shù)據(jù)類型nets (ii)wire Y; / declarationassign Y = A & B; wand Y; / declarationassign Y = A; assign Y = B;wor Y; / declarationassign Y = A; assign Y = B;drtri Y; / declarationassign Y = (dr) ? A : z; 第23頁(yè)/

11、共57頁(yè)第24頁(yè)/共57頁(yè)第25頁(yè)/共57頁(yè)第26頁(yè)/共57頁(yè)Reg型 可以用來(lái)存儲(chǔ)數(shù)據(jù) 可用來(lái)表示always模塊內(nèi)的指定信號(hào) Only one type: regreg A, C; / declaration/ assignments are always done inside a procedureA = 1;C = A; / C gets the logical value 1A = 0; / C is still 1C = 0; / C is now 0 寄存器保持最后一次的賦值第27頁(yè)/共57頁(yè)第28頁(yè)/共57頁(yè)第29頁(yè)/共57頁(yè)端口定義modulereg or netnetmo

12、dulereg or netnetmodulenetnet Inputs Outputs Inouts第30頁(yè)/共57頁(yè)矢量 代表總線buswire 3:0 busA;reg 1:4 busB; reg 1:0 busC; 左邊是最大位 MS bit Slice managementbusC1 = busA2;busC0 = busA1; 矢量賦值 (by position!)busB4 = busA3;busB3 = busA2;busB2 = busA1;busB1 = busA0;busB = busA; busC = busA2:1;第31頁(yè)/共57頁(yè)寄存器類型：整數(shù)和實(shí)數(shù) Decla

13、rationinteger i, k;real r; 在一個(gè)過(guò)程塊中，實(shí)數(shù)可以當(dāng)做寄存器用i = 1; / assignments occur inside procedurer = 2.9;k = r; / k is rounded to 3 整數(shù)沒(méi)有默認(rèn)的初始值! 實(shí)數(shù)的默認(rèn)初始值為0.0第32頁(yè)/共57頁(yè)第33頁(yè)/共57頁(yè)寄存器類型：timen不對(duì)應(yīng)具體的硬件電路nDeclarationntime my_time;nUse inside procedurenmy_time = $time; / get current sim timenSimulation runs at simulat

14、ion time, not real time第34頁(yè)/共57頁(yè)標(biāo)量和矢量n 標(biāo)量 線寬為1的連線類，或位寬為1的寄存器類 wire a, b, c; reg d, e, f;n 矢量 線寬大于1的連線類，或位寬大于1的寄存器類 wire7:0 bus_a,bus_b; reg15:0 reg_d,reg_e;第35頁(yè)/共57頁(yè)矢量 (i) Syntaxinteger count1:5; / 5 integersreg var-15:16; / 32 1-bit regsreg 7:0 mem0:1023; / 1024 8-bit regs Accessing array elements

15、Entire element: mem10 = 8b 10101010; Element subfield (needs temp storage):reg 7:0 temp;.temp = mem10;var6 = temp2;第36頁(yè)/共57頁(yè)矢量 (ii) Limitation: Cannot access array subfield or entire array at oncevar2:9 = ?; / WRONG!var = ?; / WRONG! No multi-dimentional arraysreg var1:10 1:100; / WRONG! Arrays dont

16、 work for the Real data typereal r1:10; / WRONG !第37頁(yè)/共57頁(yè)字符串n Implemented with regs:nreg 8*13:1 string_val; / can hold up to 13 charsn.nstring_val = “Hello Verilog”;nstring_val = “hello”; / MS Bytes are filled with 0nstring_val = “I am overflowed”; / “I ” is truncatedn 特殊字符:nn換行nttab鍵n%n反斜桿n“引號(hào)第38頁(yè)

17、/共57頁(yè)參數(shù)定義n 用文本來(lái)替代數(shù)字量n 格式 parameter parameter msb=7，lsb=0；n 方便閱讀，可參數(shù)化設(shè)計(jì)第39頁(yè)/共57頁(yè)宏替換n用文本（宏名）替換verilog描述內(nèi)容n格式： 結(jié)束無(wú)分號(hào)（；） 引用中宏名前加“” 宏名習(xí)慣用大寫 define define MSB=7 define LSB=0 regMSB:LSB a; 第40頁(yè)/共57頁(yè)模擬時(shí)間定標(biāo)(i)n對(duì)模擬器的時(shí)間單位和時(shí)間計(jì)算精度進(jìn)行定標(biāo)n格式 timescale / 計(jì)時(shí)單位：模擬器的模擬單位時(shí)間 計(jì)時(shí)精度：模擬過(guò)程中的延時(shí)量計(jì)時(shí)精度 結(jié)束沒(méi)有“；” timescale 1ns/1ps第41

18、頁(yè)/共57頁(yè)模擬時(shí)間定標(biāo)(ii) timescale 1ns/ 100psmodule AndFunc (Z, A, B);output Z;input A, B;and # (5.22, 6.17 ) Al (Z, A, B); /規(guī)定了上升及下降時(shí)延值。endmodule時(shí)延值5.22對(duì)應(yīng)5.2 ns, 時(shí)延6.17對(duì)應(yīng)6.2 ns第42頁(yè)/共57頁(yè)系統(tǒng)命令n 輸出控制：$display,$write,$monitorn 模擬時(shí)標(biāo)：$time,realtimen 進(jìn)程控制：$finish, $stopn 文件讀寫：$readmem第43頁(yè)/共57頁(yè)運(yùn)算符 表示物理量間的相互作用關(guān)系，反映硬

19、件電路的物理特性。第44頁(yè)/共57頁(yè)算術(shù)運(yùn)算符(i)n+, -, *, /, %n如果某一個(gè)操作數(shù)是不定態(tài)x ，則整個(gè)結(jié)果頁(yè)為不定態(tài) xn無(wú)符號(hào)reg:無(wú)符號(hào)寄存器regs可為負(fù)數(shù)賦值，但是在算術(shù)運(yùn)算中被當(dāng)做是無(wú)符號(hào)數(shù)處理。nreg 15:0 regA;n.nregA = -4d12;/ stored as 216-12 = 65524nregA/3evaluates to 21861第45頁(yè)/共57頁(yè)算術(shù)運(yùn)算符(ii)n無(wú)符號(hào)整數(shù) integers:n可以賦值負(fù)數(shù) ndifferent treatment depending on base specification or notn reg

20、 15:0 regA;n integer intA;n .n intA = -12/3; / evaluates to -4 (no base spec)n intA = -d12/3; / evaluates to 1431655761 (base spec)第46頁(yè)/共57頁(yè)位運(yùn)算符(i)按位運(yùn)算，兩個(gè)操作數(shù)不等長(zhǎng)時(shí)，運(yùn)算結(jié)果按長(zhǎng)操作數(shù)補(bǔ)0或x & 按位與運(yùn)算 | 按位或運(yùn)算 按位取反運(yùn)算 按位異或運(yùn)算 or 按位同或運(yùn)算第47頁(yè)/共57頁(yè)位運(yùn)算符(ii)c = a;c = a & b; a = 4b1010;b = 4b1100; a = 4b1010;b = 2b11;c = a b;第48頁(yè)/共57頁(yè)縮位運(yùn)算符單目運(yùn)算符，對(duì)操作數(shù)按位進(jìn)行邏輯運(yùn)算，結(jié)果是一位值！n& 與ANDn| 或ORn 異或XORn& 與非NANDn| 或非NORn or 同或 XNORnOne multi-bit operand One single-bit resultna = 4b1001; n.nc = |a; / c = 1|0|0|1 = 1第49頁(yè)/共57頁(yè)邏輯運(yùn)算符表示運(yùn)算