可編程邏輯器件數(shù)字鐘

1、可編程邏輯器件及其應(yīng)用 一 設(shè)計(jì)要求用Verilog HDL設(shè)計(jì)一個(gè)多功能數(shù)字鐘基本功能描述：1. 時(shí)鐘功能：包括時(shí)、分、秒的顯示；2. 定時(shí)與鬧鐘功能：能在設(shè)定的時(shí)間發(fā)出鬧鈴音；3. 校時(shí)功能：能非常方便地對(duì)小時(shí)、分鐘和秒進(jìn)行手動(dòng)調(diào)整以校準(zhǔn)時(shí)間；4. 整點(diǎn)報(bào)時(shí)功能：每逢整點(diǎn)，產(chǎn)生“嘀嘀嘀嘀-嘟”，四短一長(zhǎng)的報(bào)時(shí)音。二 仿真環(huán)境 用Modelsim進(jìn)行編譯和仿真，工程文件在clocknew1文件夾中。三 結(jié)果說(shuō)明 此次設(shè)計(jì)實(shí)現(xiàn)了數(shù)字鐘的基本功能，能夠進(jìn)行時(shí)分秒的計(jì)時(shí)，校準(zhǔn)，能夠整點(diǎn)報(bào)時(shí)，在設(shè)定的時(shí)間實(shí)現(xiàn)響鈴功能。此次設(shè)計(jì)對(duì)各種功能進(jìn)行了分模塊設(shè)計(jì)，記數(shù)模塊中，對(duì)秒位，分位進(jìn)行60位記數(shù)，小時(shí)模

2、塊進(jìn)行24位記數(shù)；同時(shí)在記數(shù)模塊中進(jìn)行校準(zhǔn)操作；報(bào)時(shí)模塊里，每逢整點(diǎn)前的59分56秒、59分57秒、59分58秒、59分59秒，和整點(diǎn)時(shí)刻，發(fā)出“嘀嘀嘀嘀-嘟”的報(bào)時(shí)聲；鬧鐘模塊里，手動(dòng)對(duì)數(shù)字鐘進(jìn)行定時(shí)，當(dāng)數(shù)字鐘的時(shí)刻與定時(shí)時(shí)刻相同時(shí)，ring=1發(fā)出響鈴聲。在以上各個(gè)功能的模塊基礎(chǔ)上，設(shè)置top頂層模塊，將以上功能綜合起來(lái)實(shí)現(xiàn)。為了驗(yàn)證數(shù)字鐘的功能，編寫(xiě)測(cè)試testench模塊，輸入時(shí)鐘#5 clk=clk，觀察各個(gè)信號(hào)輸出。四 仿真結(jié)果圖1仿真整體效果圖圖2當(dāng)reset鍵為0時(shí)，開(kāi)始計(jì)數(shù)圖3 秒位計(jì)數(shù)圖4 分鐘計(jì)數(shù)圖5 小時(shí)位計(jì)數(shù)圖6 整點(diǎn)報(bào)時(shí)功能圖7 定時(shí)響鈴功能圖8 校時(shí)功能，校時(shí)使能

3、鍵為1，停止計(jì)數(shù)，校時(shí)圖9 校時(shí)使能鍵為0，按校好的時(shí)間繼續(xù)計(jì)數(shù)五 設(shè)計(jì)代碼/頂層模塊module top ( /input clk,reset012,dssl,dssh,dsml,dsmh,dshl,dshh,dingshi, ksec,kmin,khour,cntsec,cntmin,cnthour, /output sl,sh,ml,mh,hl,hh,di,do,ring ); input clk; input reset012; input 3:0 dssl,dssh,dsml,dsmh,dshl,dshh; input ksec,kmin,khour; input 7:0cntsec

4、,cntmin,cnthour; input dingshi; output3:0 sl,sh,ml,mh,hl,hh; wire 3:0 sl,sh,ml,mh,hl,hh; output di,do,ring; wire di,do,ring; wire 3:0 c,d,e,f,g,j; wire a,b; /對(duì)模塊立化 second my_second (.clk(clk),.reset(reset012),.sh(d),.sl(c),.co(a),.ksec(ksec),.cntsec(cntsec); minute my_minute (.reset1(reset012),.mh(f

5、),.ml(e),.clk1(a),.co1(b),.kmin(kmin),.cntmin(cntmin); hour my_hour (.reset2(reset012),.hh(j),.hl(g),.clk2(b),.khour(khour),.cnthour(cnthour); baoshi my_baoshi (.bssl(c),.bssh(d),.bsml(e),.bsmh(f),.bshl(g),.bshh(j),.di(di),.do(do); naozhong my_naozhong (.dssl(dssl),.dssh(dssh),.dsml(dsml),.dsmh(dsmh

6、),.dshl(dshl),.dshh(dshh), .clksl(c),.clksh(d),.clkml(e),.clkmh(f),.clkhl(g),.clkhh(j),.dingshi(dingshi),.ring(ring); assign sl = c;assign sh = d;assign ml = e;assign mh = f;assign hl = g;assign hh = j;endmodule /秒位計(jì)數(shù)模塊module second(clk,reset,sh,sl,co,ksec,cntsec);input clk; input reset; output3:0sh

7、,sl; / 秒位輸出的十位和個(gè)位reg3:0sh,sl;output co; /進(jìn)位reg co;input ksec;input7:0cntsec;reg7:0cnt; /計(jì)數(shù)器/遇到時(shí)鐘上升沿或置位下降沿觸發(fā)always(posedge clk or negedge reset) begin if(ksec=1) begin /校準(zhǔn) cnt<=cntsec; end else if(reset=0) begin /復(fù)位 sl<=4'd0;sh<=4'd0;cnt<=0;end else begin /計(jì)數(shù)到60，進(jìn)位 if(cnt=8'd6

8、0) beginsl<=4'd0;sh<=4'd0;cnt<=8'd0;co<=1'd1;endelse begin /小于60，繼續(xù)計(jì)數(shù)cnt<=cnt+1;co<=1'd0 ;sh<=cnt/10; /十位sl<=cnt%10; /個(gè)位 endendend endmodule/分鐘計(jì)數(shù)模塊module minute(reset1,mh,ml,clk1,co1,kmin,cntmin);input reset1; /復(fù)位input clk1; /時(shí)鐘output3:0mh,ml; / 分鐘十位和個(gè)位reg

9、3:0mh,ml;output co1; /進(jìn)位reg co1;input kmin;input7:0cntmin;reg7:0cnt1; /計(jì)數(shù)器/遇到時(shí)鐘和復(fù)位觸發(fā)always(negedge clk1 or negedge reset1) begin if(kmin=1) begin /校準(zhǔn) cnt1<=cntmin; end else begin if(reset1=0) begin /復(fù)位ml<=0;mh<=0;cnt1<=0; end else if(cnt1=8'd60) begin /計(jì)數(shù)到60，進(jìn)位。重新計(jì)數(shù)ml<=4'd0;mh

10、<=4'd0;cnt1<=8'd0;co1<=1'd1;endelse begin /計(jì)數(shù)不到60繼續(xù)cnt1<=cnt1+1;co1<=1'd0 ;mh<=cnt1/10; /十位ml<=cnt1%10; /個(gè)位endendend endmodule/小時(shí)計(jì)數(shù)模塊module hour(reset2,hh,hl,clk2,khour,cnthour);input clk2; /時(shí)鐘input reset2; /復(fù)位output3:0hh,hl; / ?reg3:0hh,hl;reg7:0cnt2; /計(jì)數(shù)器input

11、khour;input7:0 cnthour;/遇到時(shí)鐘和復(fù)位觸發(fā)always(negedge clk2 or negedge reset2) begin if(khour=1) begin /校準(zhǔn) cnt2<=cnthour; end else if(reset2=0) begin /復(fù)位 hl<=0; hh<=0; cnt2<=0; end else begin /計(jì)數(shù)到24重新計(jì)數(shù) if(cnt2=8'd24) begin hl<=4'd0; hh<=4'd0; cnt2<=8'd0; end else begin

12、 /計(jì)數(shù)不到24繼續(xù) cnt2<=cnt2+1; hh<=cnt2/10; /十位 hl<=cnt2%10; /個(gè)位 end endend endmodule /鬧鐘模塊，在設(shè)定的時(shí)間響鈴module naozhong(dssl,dssh,dsml,dsmh,dshl,dshh, /input clksl,clksh,clkml,clkmh,clkhl,clkhh, /input dingshi,ring);/手動(dòng)定時(shí)input3:0dssl,dssh,dsml,dsmh,dshl,dshh; input3:0clksl,clksh,clkml,clkmh,clkhl,clk

13、hh;reg3:0naosl,naosh,naoml,naomh,naohl,naohh;input dingshi; /定時(shí)使能鍵output ring; /響鈴鍵reg ring;/定時(shí)變化觸發(fā)always(dssl or dssh or dsml or dsmh or dshl or dshh) begin if(dingshi=1) begin naosl<=dssl; naosh<=dssh; naoml<=dsml; naomh<=dsmh; naohl<=dshl; naohh<=dshh; end else begin naosl<=n

14、aosl; naosh<=naosh; naoml<=naoml; naomh<=naomh; naohl<=naohl; naohh<=naohh; end end /時(shí)鐘變化觸發(fā)，當(dāng)數(shù)字鐘時(shí)鐘與定時(shí)時(shí)鐘相同時(shí)響鈴； always(clksl or clksh or clkml or clkmh or clkhl or clkhh or naosl or naosh or naoml or naomh or naohl or naohh) begin if(naosl=clksl)&&(naosh=clksh)&&(naoml=c

15、lkml)&&(naomh=clkmh) &&(naohl=clkhl)&&(naohh=clkhh) ring<=1'd1; else ring<=1'd0; endendmodule/整點(diǎn)報(bào)時(shí)模塊module baoshi(bssl,bssh,bsml,bsmh,bshl,bshh,di,do); input3:0bssl,bssh,bsml,bsmh,bshl,bshh; output di,do; reg di,do; /在59分56秒 59分57秒 59分58秒 59分59秒發(fā)出嘀嘀嘀嘀的聲音 always(

16、bssl or bssh or bsml or bsmh or bshl or bshh) begin if( ( bsmh=4'd5 ) && ( bsml=4'd9 ) && ( bssh=4'd5 ) && ( bssl=4'd6 ) ) di<=1'd1; else if( ( bsmh=4'd5 ) && ( bsml=4'd9 ) && ( bssh=4'd5 )&& ( bssl=4'd7 ) ) di<

17、;=1'd1; else if( (bsmh=4'd5 ) && ( bsml=4'd9 ) &&( bssh=4'd5 ) && ( bssl=4'd8 ) ) di<=1'd1; else if( ( bsmh=4'd5 ) && ( bsml=4'd9 ) && ( bssh=4'd5 ) && ( bssl=4'd8 ) ) di<=1'd1; else di<=1'd0; en

18、d /整點(diǎn)發(fā)出嘟的聲音 always(bssl or bssh or bsml or bsmh or bshl or bshh) begin if(bsmh=4'd0)&&(bsml=4'd0)&&(bssh=4'd0)&&(bssl=4'd0) do<=1'd1; else do<=1'd0; endendmodule /測(cè)試模塊timescale 1ns/100psmodule testbench; reg clk; reg reset012; reg dingshi; reg 3:

19、0 dssl,dssh,dsml,dsmh,dshl,dshh; reg 7:0 cntsec,cntmin,cnthour; reg ksec,kmin,khour; wire3:0 sl,sh,ml,mh,hl,hh; wire di,do,ring; initial /set simulate time begin clk=0; reset012=1; dingshi = 0; #100 dingshi = 1; #100 dingshi = 0; #1000 reset012=0; #1000 reset012 = 1; #3000000 $stop; end initial begin /when dingshi=1,you can set dingshi; dingshi=1'd1; end initial begin cntsec=8'd55; ksec=0; #1000000 ksec=1; #500000 ksec=0; end initi