先進(jìn)芯片封裝知識(shí)介紹.

1、Advaneed Packaging TechOutline Package Development Trend 3D Package WLCSP & Flip Chip PackagePackage Development Trend90 nmMoore Law2nd GenerationBGA / Fan-In PoP二二二二二二二PPonturi；SOPCOL QfHCu PillarCu WireHybrid SiPBD sUcklAodulePiP&PbPSBS aWLP3D aWLPWLCSP/iCSP Std.M O W kJ tZv* V* V> Lf W

2、/ TSV mterwer45 / 40 nm 32 / 28 nmwire bondPac-aee3rd GenerationFC & 3D SiP & Innovation PkgLKLfLF ELKricePBGAcost performance1984199040nm28 nm 1 PlatingaWLPOieFBGA _MCP . Stacked Die FCKCM Hybrid FOWB MocXjIc System IntegrationPoP3 D»e»DttcrcU200020082009201020112012COL- VSOP(2 di

3、es) DOVSOPCOL- VSOP(2 dies) DOVSOPPackage Development TrendCOL- VSOP(2 dies) DOVSOPCOL- VSOP(2 dies) DOVSOP SO Family QFP Family BGA FamilyCOL- VSOP(2 dies) DOVSOPCOL- VSOP(2 dies) DOVSOPTSOPEDHS.BGA MPBGAPOPBGADHSQfPEW1S-QFPLQFPFCBGACOL-TSOP (4 dies) COL TSOP (8 di") Balance moldUn-balanco mol

4、dDHSXQFPE-PAD LQFPEHS-FCBGA MP4：CBGA Terminator FCBGAVSOPTQFPVQFPEBGACOL- VSOP(2 dies) DOVSOPPackage Development Trend CSP Family Memory Card SiP ModuleMini SD Micro SD RSMMC MMC M»CfOWin *BT ModuloTFBGAS-TFBGA WUM丿XFBGA COSBGA1WLC5PKDWimax ModuleGPS ModuleWiFi BT $ FM Radio Module3D Package3D

5、Package3D Package Introduction8HietCSP 4- S-CSPPackage onPackage (PoP)Stacki ngUOQe蚩 u- -euoloun 亠Multi ChipStacketCSP Stack3 S CSP4SS-SCSPSSCSP2 Chip Stack Flip Chip & Wirebond2 Chip Stack WirebondUltra thin StackStacked DieProcess flow of FOW and Film Spacer If FOW spacer is applied to same oi

6、zc die attach/ the film spacer cut & place machine(modulc) is not required, UPH can be in<reased, and wire bond ability for top die will be improved by supported wire bonding area(no die overhang).device attachCurrvnt same size die atUch nMhod Wth film spacerFilm spacer attachb b 6 du bbBotto

7、m die :Top die : 3SOr<OOx3mlFOW materilBottom dieNew same size attach method vMth FOW spacerTSV TSV (Through Silicon Via)A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is imports nt in creating 3D packages an

8、d 3D integrated circuits A3D package (System in Package, Chip Stack MCMZ etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less spaceIn most 3D packages, the stacked chips are wired together along their edges This edge wiring slightly increases the length

9、and width of the package and usually requires an extra interposer'* layer between the chips.In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips The resulting package has no acded length or thicknessWire Bonding Stacked D

10、iePOP What's PoP? PoP is Package on PackageTop and bottom packages are tested separately by device manufacturer or subcon.Logic package Assembly & TestMemory package Assembly & TestPoP PoP Core Tech no logyPin Gate MoldWafer ThinningPoP AmkorzsTMV PoPAllows for warpage reduction by utili

11、zing fully-molded structure More compatible with substrate thickness reduction Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size / package size ratio Compatible with flip chip, wire bond, or stacked die configurations Cost effective compare

12、d to alternative next generation solutionsTMV PoP Cross SectionsThrough Mold Via1Top viewBottom viewB2PoP Process Flow of TMV PoPBall Placement on top surfaceDie BondI Laser drillingLaser beamThermal effectBall Placement on bottomSingulation Final Visual InspectionBase M'tlp* Memory die Analog d

13、ie Digital die Digital(Btm die) + Analog(Middle die) + Memory(Top pkg) Potable Digital Gadget Cellular Phone, Digital St川 Camera, Potable Game Unit Why PiP?/Easy system integration"Flexible memory configuration丁 100% memory KGD/Thinner package than POP"High IO interconnection than POPi 丁Sm

14、all footprint in CSP format)丨“ il * IU IIOO OO CJIt has standard ball size and pitch PiP Core Tech no logyConstructed with: Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnction Mold encapsulationWafer ThinningPiP PiP-W/B PiPand FC PiPWB PIPFC PIPWLCSP & Flip Chip P

15、ackageWLCSP What is WLCSP?WLCSP(Wafer Level Chip Scale Packaging), is not same as traditional packaging method (dicing packagitesting, package size is at least 20% increased compared to die size).WLCSP is packaging and testing on wafer base, and dicing later. So the package size is exactly same as b

16、are die size WLCSP can make ultra small package size, and high electrical performance because of the short interconnectionBumpVto at l.'O,Cu RDLUBM StudCu RDPassivation OpeningUBM StudBump and Polymer 2 ar* no< shown for clarityPolymor 1 openingPolymoc 1Nitrid*WLCSP Why WLCSP?- Snidllebl pack

17、age bize; WLCSP liave lhe bnidllebl package bize dgdiribl die bize Su il hd、widely ube in mobile devices一 High electrical performance: because of the short and thick trace routing in RDL, it gives high SI and reduced IR drop- High thermal performance: since there is no plastic or ceramic molding cap

18、, heat from die can easily spread out- Low cost: no need substrate, only one time testing WLCSP's disadvantage一 Because of the die size and pin pitch limitation, IO quantity is limited (usually less than 50pins).一 Because of the RDL, stagger IO is not allowed for WLCSP.RDL RDL: Redistribution La

19、yer A redistribution layer (RDL) is a set of traces built up on a wafer's active surface to re-route the bond pads This is done to in crease the spaci ng between each interc onn ectio n(bump).WLCSP Process Flow of WLCSPPBO, Photo ProcessUBM Platinq & EtchPSV(SI3N4)UBMRDL Plating & EtchPB

20、02 Photo ProcessRDL trace (Cu)PBO2 1廠LPBO1Silicon = Process Flow of WLCSPWfer IttfMngWfer BumpinqUBM rrunufjKzturcWLCSP mdrhbigWafer LscrMurium)OptionalFlip Chip PackageMCM-FCBGA(Multi-Chip-Module FCB6A)lllkPI-EHS-MP-FCBGA(Passive Integrated Exposed Heit Sink Multi Package Flip Chip)Bump4 electropla

21、ting (PbSn)5. resist stripping6. plating base etch and refk>w4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w2000200220042006 20()8 20102012Wafer Size1 150/200mm1i. 300mmiii4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w4 electroplating (Pb

22、Sn)5. resist stripping6. plating base etch and refk>wPlated4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w-Polyimide Plated EU/LF - 會(huì)-Poly imide PUtedRedisttibution Polyimid< Printed - LF P

23、oly imide PMtcd LF4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>wBump DevelopmentSolder Bumping (mushroom)4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>w4 electroplat

24、ing (PbSn)5. resist stripping6. plating base etch and refk>w1 passivation layer3. exposure development pm2. sputter UBM and coat resist4 electroplating (PbSn)5. resist stripping6. plating base etch and refk>wBump DevelopmentGold Bumping*1. passivation layer4. resist development2. sputter UBM a

25、nd coat resist5 electroplating6 resist stripping and etching of plating base4. electroplating (Cu + solder)5 resist stripping6 platmg base etch and refiow4. electroplating (Cu + solder)5 resist stripping6 platmg base etch and refiowBump Development4. electroplating (Cu + solder)5 resist stripping6 p

26、latmg base etch and refiow4. electroplating (Cu + solder)5 resist stripping6 platmg base etch and refiowCopper Posts1. passivation layer2 sputter UBM and coat re/st3 exposure developmentCu4. electroplating (Cu + solder)5 resist stripping6 platmg base etch and refiowC4 Flip Chip Whatzs C4 Flip Chip?

27、C4 is: Controlled Collapsed Chip Connection Chip is connected to substrate by RDL and Bump Bump material type: solder, goldSiot«eCMpFCCSPMCfCBGAQHFCrc POPCopper Pillar Bump1 50um135umo1 80um160umSolder bump120um2010Available20092011 Main FeaturesC4 Flip Chip BGA Ball Pitch:0.4mm - 1.27mm Packag

28、e size: up to 55mmx55mm Substrate layer： 4-16 Layers Ball Count: up to 2912 Target Market: CPU. FPGA. Processor > Chipset. Memory Router、Switches, and DSP etc. Main Benefits Reduced Signal Inductance Reduced Power/Ground Inductance Higher Signal Density Die Shrink & Reduced Package Footprint2.0*3.5mmThermal CompoundBT / Build-up Sub»tid(eSolder Bump Die