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1、High Performance Power Combi ControllerTDA 168881Overview1.1FeaturesPFC SectionIEC 1000-3 compliantAdditional operation mode as auxiliary power supply Fast, soft switching totem pole gate drive (1 A) Dual loop control (average current and voltage sensing)Leading edge triggered pulse width modulation

2、 Peak current limitationTopologies of PFC preconverter are boost or flyback Continuous/discontinuous mode possible94%um duty cycleSectionImproved current mode controlFast, soft switching totem pole gate drive (1 A) Soft-start managementTrailing edge triggered pulse width modulationTopologies ofconve

3、rter are feed forward or flyback50%fum duty cycle to prevent transformer saturation= fPFC New typeSemiconductor Group1Datasheet DownloadData Sheet 1998-05-06TypeOrdering CodePackageTDA 16888Q67000-A9284-X201-K5P-DIP-20-5TDA 16888GQ67000-A9310-A702P-DSO-20-1P-DSO-20-1P-DIP-20-5TDA 16888Special Featur

4、esHigh power factorTypical 50 mA start-up supply current Low quiescent current (15 mA)Undervoltage lockout with internal stand-by operationInternally synchronized fixed operating frequency ranging from 15 kHz to 200 kHz External synchronization possibleShutdown of both outputs externally triggerable

5、 Peak current limitationOvervoltageAverage currensing by noise filtering1.2General RemarksThe TDA 16888 comprises the complete control for power factor controlled switchedmode powers. With its PFC andsection being internally synchronized, itapplies for off-line converters with input voltages ranging

6、 from 90 V to 270 V.While the preferred topologies of the PFC preconverter are boost or flyback, the section can be designed as forward or flyback converter. In order to achieve minimal linecurrent gaps theum duty cycle of the PFC is about 94%. Theum duty cycleof the, however, is limited to 50% to p

7、revent transformer saturation.Semiconductor Group2Datasheet DownloadData Sheet 1998-05-06TDA 16888Figure 1Pin Configuration (top view)Semiconductor Group3Datasheet DownloadData Sheet 1998-05-06P-DIP-20-5P-DSO-20-1PFC IAC120AUX VSVREF2PFC VSPFC CCPFC VCPFC IAC1AUX VSPFC CSPFC FBVREF2PFC VSPFC CC3PFC

8、VCGND SROSCPFC CS4PFC FBGND S516ROSCPFC CL6RMPPFC CL615RMPGND714INGNDINPFC OUT813SSPFC OUTSSVCC12SYNC OUT11CSVCCSYNCAEP02486OUT1011CSAEP02461TDA 168881.3Pin Definitions and FunctionsSemiconductor Group4Datasheet DownloadData Sheet 1998-05-06Pin No.SymbolFunction1PFC IACAC line voltage sensing input2

9、VREF7.5 V reference3PFCFC current loop compensation4PFC CSPFC currense5GND SGround sensing input6PFC CLSensing input for PFC current limitation7GNDGround8PFC OUTPFC driver output9VCCSupply voltage10OUTdriver output11CScurrense12SYNCOscillator synchronization input13SSsoft-start14INoutput voltage sen

10、sing input15RMPvoltage ramp16ROSCOscillator frequency set-up17PFC FBPFC voltage loop feedback18PFC VCPFC voltage loop compensation19PFC VSPFC output voltage sensing input20AUX VSAuxiliary power supply voltage sensePFC PFCIACFBPFC VCPFC CSAUX VSGND SPFC CCPFC VSPFC CLPFC OUTV CC1171841.2 V205319698OT

11、A3OP1C3+_VS5 V1 VD3OTA1VSD4OP2C1M5 V2R 2+_QFF1M&R S&10 kWM1Z1M 3D1D2OTA2C2+_5.5 V1 VC4C6VSZ317.5 V4 V6 V5.5 VVSUndervoltage Lockout 11 V-14 VOsc7.4 VFF21C7I1S RPower Management3&&Z2Voltage Reference7.5 V (Output Disable)6 V0.C80.4C9V1OP31 V1.5 VR1+_510 kWC10R 3100 kWBias Control0.4 V

12、1521216131411710V REFSYNC ROSCGNDSSINRMPCSOUTAEB02357TDA 168881.4Block Diagram1Figure 2Semiconductor Group5Datasheet DownloadData Sheet 1998-05-060 mA45 VV C5TDA 168882Functional DescriptionPower SupplyThe TDA 16888 is protected Zener diode Z3 at pin 9 (VCC) and ESD circuitry.overvoltages typically

13、above 17.5 V by an internal electrostatic discharging at any pin by specialBy means of its power management the TDA 16888 will switch from internal stand-by, which is characterized by negligible current consumption, to operation mode as soon as a supply voltage threshold of 14 V at pin 9 (VCC) is ex

14、ceeded. To avoid uncontrolled ringing at switch-over an undervoltage lockout is implemented, which will cause the power management to switch from operation mode to internal stand-by as soon as thesupply voltage falls below a threshold of 11 V. Therefore, even if the supply voltage will fall below 14

15、 V, operation mode will be maintained as long as the supply voltage is well above 11 V.As soon as the supply voltage has stabilized, which is determined by the TDA 16888spower management and its soft-start feature at pin 13 ( be enabled by means of its internal bias control.SS), thesection willCircu

16、itryBoth PFC andsection are equipped with a fast overvoltage(C6)sensing at pin 19 (PFC VS), which when being activated will immediately shut down both gate drives. In addition to improve the PFC sections load regulation it uses a fast but softovervoltage(OTA2) prior to the one described above, which

17、 when beingactivated will cause a well controlled throttling of the multiplier output QM.In case an undervoltage of the PFC output voltage is detected at pin 19 (PFC VS) bycomparator C4 the gate drive of thesection will be shut down in order to reducethe load current and to increase the PFC output v

18、oltage. This undervoltage shutdown has to be prior to the undervoltage lockout of the internal power management and therefo as to be bound to a threshold voltage at pin 9 (VCC) well above 11 V.In order to prevent the external circuitry from destruction the PFC output PFC OUT (pin 8) will immediately

19、 be switched off by comparator C2, if the voltage at pin 19 (PFC VS) drops to ground caused by a broken wire. In a similar way measures are taken to handle a broken wire at any other pin in order to ensure a safe operation of the IC and its adjoining circuitry.If necessary both outputs, PFC OUT (pin

20、 8) andOUT (pin 10), can be shutdownon external request. This is accomplished by shorting the external reference voltage at pin 2 (VREF) to ground. To protect the external reference, it is equipped with a foldback characteristic, which will cut down the output current when VREF (pin 2) is shorted (s

21、ee Figure 4).Semiconductor Group6Datasheet DownloadData Sheet 1998-05-06TDA 16888Both PFC andsection are equipped with a peak current limitation, which is realizedby the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (CS)respectively. When being activated this current limitation will imm

22、ediately shut down therespective gate drive PFC OUT (pin 8) orOUT (pin 10).Finally each pin is protectedelectrostatic discharge.Oscillator/SynchronizationThe PFC andclock signals as well as the PFC voltage ramp are synchronized bythe internal oscillator (see Figure 18). The oscillators frequency is

23、set by an external resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a high electromagnetic interferences. In order to ensure superior precisionof the clock frequency, the clock signal CLK OSC

24、 is derived from a triangular instead of a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillators clock signal CLK OSC is halved by a D-latchbefore being fed into the PFC andThe ramp signal of the PFC sectionsection respective

25、ly (see Figure 18).VPFC RMPis composed of a slowly falling and asteeply rising edge. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pin 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC

26、 CC).The oscillator can be synchronized with an external clock signald at pin 12(SYNC). However, since the oscillators frequency is halved before being fed into thePFC andsection, a synchronization frequency being twice the operating frequencyis recommended. As long as the synchronization signal is

27、H the oscillators triangularVOSCsignalis interrupted and its clock signal CLK OSC is H (see Figure 19 andFigure 20). However, as soon as the external clock changes from H to L the oscillator isreleased. Correspondingly, by means of an external clock signald at pin 12(SYNC) the oscillator frequency f

28、OSC set by an external resistor at pin 16 (ROSC) can bevaried on principle only within the range from 0.66 fOSC to 2 fOSC. If the oscillator has to be synchronized over a wider frequency range, a synchronization by means of the sink current at pin 16 (ROSC) has to be preferred to a synchronization b

29、y means of pin 12 (SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanentlyshutdown both PFC andsection. It can be used to halt the oscillatorzing theprevailing state of both drivers but does not allow to automatically shut them down. A shutdown can be achieved by shorting pin 2 (V

30、REF) to ground, instead.Finally, In order to reduce the overall current consumption under low load conditions, theoscillator frequency itself is halved as long as the voltage at pin 13 (SS) is lessthan 0.4 V (disabledsection).Semiconductor Group7Datasheet DownloadData Sheet 1998-05-06TDA 16888PFC Se

31、ctionAt normal operation the PFC section operates with dual loop control. An inner loop, which includes OP2, C1, FF1 and the PFCs driver, controls the shape of the line current by average current control enabling either continuous or discontinuous operation. By the outer loop, which is supported by

32、OP1, the multiplier, OP2, C1, FF1 and the PFC's driver, the PFC output voltage is controlled. Furthermore there is a third control loop composed of OTA1, OP2, C1, FF1 and the PFCs driver, which allows the PFC section to beoperated as an auxiliary power supply even when thesection is disabled. Wi

33、thdisabledsection, however, the PFC section is operated with half of its nominaloperating frequency in order to reduce the overall current consumption.Based on a pulse-width-modulation, which is leading edge triggered with respect to the internal clock reference CLK OUT and which is trailing edge mo

34、dulated according to the PFC ramp signal VPFC RMP and the output voltage of OP2 VPFC CC (see Figure 18), thePFC section is designed for a current gaps.um duty cycle of ca. 94% to achieve minimal lineSectionsection is equipped with improved current mode control containing effectiveTheslope compensati

35、on as well as enhanced spike suppression in contrast to the commonly used leading edge current blanking. This is achieved by the chain of operational amplifier OP3, voltage source V1 and the 1st order low pass filter composed of R1 and an externalcapacitor, which is connected to pin 15 (RMP). For cr

36、osstalk suppression betweenPFC andsection a signal-to-noise ratio comparable to voltage mode controlleds is set by operational amplifier OP3 perfora fivefold amplification of theload current, which is sensed by an external shunt resistor. In order to simultaneously perform effective slope compensati

37、on and to suppress leading spikes, which are due to parasitic capacitances being discharged whenever the power transistor is switched on, the resulting signal is subsequently increased by the constant voltage of V1 and finally fed into the 1st order low pass filter. The peak ramp voltage, that in th

38、is way can be reached, amounts to ca. 6.5 V. By combination of voltage source V1 and the following low pass filter a basic ramp (step response) with a leading notch is created, which will fully compensate a leading spike (see Figure 12) provided, the external capacitor atpin 15 (RMP) and the externa

39、l currensing shunt resistor are scaled properly.Semiconductor Group8Datasheet DownloadData Sheet 1998-05-06TDA 16888The pulse-width-modulation of thesection is trailing edge modulated according toramp signal VRMP) and the input voltage Vthepin 14 (at pin 15 (IN atRMPIN) (see Figure 18). In contrast

40、to the PFC section, however, the pulse-width-modulation of thesection is trailing edge triggered with respect to theinternal clock reference CLK OUT in order to avoid undesirable electromagneticinterference of both sections. Moreover the to 50% to prevent transformer saturation.um duty cycle of thei

41、s limitedBy means of the above mentioned improved current mode control a stable pulse-width-modulation from conditions the ground.um load down to no load is achieved. Finally, in case of no loadsection may as well be disabled by shorting pin 13 (SS) toSemiconductor Group9Datasheet DownloadData Sheet

42、 1998-05-06TDA 168883Functional Block DescriptionGate DriveBoth PFC andsection use fast totem pole gate drives at pin 8 (PFC OUT) andpin 10 (OUT) respectively, which are designed to avoid cross conduction currentsand which are equipped with Zener diodes (Z1, Z2) in order to improve the control of th

43、eattached power transistors as well as to protect themundesirable gateovervoltages. At voltages below the undervoltage lockout threshold these gate drives are active low. In order to keep the switching losses of the involved power diodes low and to minimize electromagnetic emissions, both gate drive

44、s are optimized for soft switching operation. This is achieved by a novel slope control of the rising edge at each drivers output (see Figure 13).OscillatorThe TDA 16888s clock signals as well as the PFC voltage ramp are provided by the internal oscillator. The oscillators frequency is set by an ext

45、ernal resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding capacitor, however, is integrated to guarantee a low current consumption and a highelectromagnetic interferences. In order to ensure superior precision of the clockfrequency, the clock signal CLK OSC is derived fr

46、om the minima anda of atriangular instead of a saw-tooth signal (see Figure 18). Furthermore, to provide a clock reference CLK OUT with exactly 50% duty cycle, the frequency of the oscillators clocksignal CLK OSC is halved by a D-latch before being fed into the PFC and respectively.sectionVPFC RMPTh

47、e ramp signal of the PFC sectionis composed of a slowly falling and asteeply rising edge, the latter of which is triggered by the rising edge of the clock reference CLK OUT. This ramp has been reversed in contrast to the common practice, in order to simultaneously allow for current measurement at pi

48、n 5 (GND S) and for external compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC). The slope of the falling edge, which in conjunction with the output of OP2 controls the pulse- width-modulation of the PFC output signal VPFC OUT, is derived from the current set by theexternal resistor at

49、 pin 16 (ROSC). In this way a constant amplitude of the ramp signal(ca. 4.5 V) is ensured. In contrast, the slope of the rising edge, which marks the minimumum duty cycle ton,max of the PFC outputblanking interval and therefore limits thesignal, is determined by an internal current source.In contras

50、t to the PFC section the ramp signal of thesection is trailing edgetriggered with respect to the internal clock reference CLK OUT to avoid undesirableelectromagnetic interference of both sections. Moreover, theum duty cycle of theis limited by the rising edge of the clock reference CLK OUT to 50% to

51、 prevent transformer saturation.Semiconductor Group10Datasheet DownloadData Sheet 1998-05-06TDA 16888The oscillator can be synchronized with an external clock signald at pin 12VOSC(SYNC). As long as this clock signal is H the oscillators triangular signalisinterrupted and its clock signal CLK OSC is

52、 H (see Figure 19 and Figure 20). However, as soon as the external clock changes from H to L the oscillator is released.Correspondingly, by means of an external clock signald at pin 12 (SYNC) theoscillator frequency fOSC set by an external resistor at pin 16 (ROSC) can be varied onprinciple only wit

53、hin the range from 0.66 fOSC to 2 fOSC. Please note, that the slope of the falling edge of the PFC ramp is not influenced by the synchronization frequency. Instead the lower voltage peak is modulated. Consequently, on the one hand at highfSYNC > fOSCsynchronization frequenciesthe amplitude of the

54、 ramp signal andcorrespondingly its signal-to-noise ratio is decreased (see Figure 19). On the other hand at low synchronization frequencies fSYNC < fOSC the lower voltage peak is clamped to the minimum ramp voltage (typ. 1.1 V), that at least can be achieved (see Figure 20), which may cause undefined PFC duty cycles as the voltage VPFC CC at pin 3 (PFC CC) drops below this threshold. However, if the