北郵電子院專業(yè)實(shí)驗(yàn)報(bào)告

1、電子工程學(xué)院ASIC專業(yè)實(shí)驗(yàn)報(bào)告班級(jí)：姓名： 學(xué)號(hào)：班內(nèi)序號(hào)：第一部分 語(yǔ)言級(jí)仿真LAB 1：簡(jiǎn)單的組合邏輯設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康恼莆栈窘M合邏輯電路的實(shí)現(xiàn)方法。二、 實(shí)驗(yàn)原理本實(shí)驗(yàn)中描述的是一個(gè)可綜合的二選一開(kāi)關(guān)，它的功能是當(dāng)sel = 0時(shí)，給出out = a，否則給出結(jié)果out = b。在Verilog HDL中，描述組合邏輯時(shí)常使用assign結(jié)構(gòu)。equal=(a=b)?1:0是一種在組合邏輯實(shí)現(xiàn)分支判斷時(shí)常用的格式。parameter定義的size參數(shù)決定位寬。測(cè)試模塊用于檢測(cè)模塊設(shè)計(jì)的是否正確，它給出模塊的輸入信號(hào)，觀察模塊的內(nèi)部信號(hào)和輸出信號(hào)。三、 源代碼mux.vmodule s

2、cale_mux(out,sel,b,a);parameter size=1;outputsize-1:0 out;inputsize-1:0b,a;input sel;assign out = (!sel)?a: (sel)?b: size1'bx;endmodulemux_test.vdefine width 8timescale 1 ns/1 nsmodule mux_test; regwidth:1a,b; wirewidth:1out; reg sel; scale_mux#(width)m1(.out(out),.sel(sel),.b(b),.a(a); initial

3、begin $monitor($stime,"sel=%b a=%b b=%b out=%b",sel,a,b,out); $dumpvars(2,mux_test); sel=0;b=width1'b0;a=width1'b1; #5sel=0;b=width1'b1;a=width1'b0; #5sel=1;b=width1'b0;a=width1'b1; #5sel=1;b=width1'b1;a=width1'b0; #5 $finish; endendmodule四、 仿真結(jié)果與波形LAB 2：簡(jiǎn)單時(shí)

4、序邏輯電路的設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康恼莆栈緯r(shí)序邏輯電路的實(shí)現(xiàn)。二、 實(shí)驗(yàn)原理在Verilog HDL中，相對(duì)于組合邏輯電路，時(shí)序邏輯電路也有規(guī)定的表述方式。在可綜合的Verilog HDL模型中，我們常使用always塊和(posedge clk)或(negedge clk)的結(jié)構(gòu)來(lái)表述時(shí)序邏輯。在always塊中，被賦值的信號(hào)都必須定義為reg型，這是由時(shí)序邏輯電路的特點(diǎn)所決定的對(duì)于reg型數(shù)據(jù)，如果未對(duì)它進(jìn)行賦值，仿真工具會(huì)認(rèn)為它是不定態(tài)。為了正確地觀察到仿真結(jié)果，在可綜合的模塊中我們通常定義一個(gè)復(fù)位信號(hào)rst-，當(dāng)它為低電平時(shí)對(duì)電路中的寄存器進(jìn)行復(fù)位。三、 源代碼counter.vtimes

5、cale 1 ns/100 psmodule counter(cnt,clk,data,rst_,load);output4:0cnt ;input 4:0data;input clk;input rst_;input load;reg 4:0cnt; always(posedge clk or negedge rst_) if(!rst_) #1.2 cnt<=0; else if(load) cnt<=#3 data; else cnt<=#4 cnt + 1; endmodulecounter_test.vtimescale 1 ns/1 nsmodule counte

6、r_test; wire4:0cnt; reg 4:0data; reg rst_; reg load; reg clk; counter c1 ( .cnt (cnt), .clk (clk), .data(data), .rst_(rst_), .load(load) ); initial begin clk=0; forever begin #10 clk=1'b1; #10 clk=1'b0; end endinitial begin $timeformat(-9,1,"ns",9); $monitor("time=%t,data=%h,c

7、lk=%b,rst_=%b,load=%b,cnt=%b", $stime,data,clk,rst_,load,cnt); $dumpvars(2,counter_test); endtask expect;input 4:0expects; if(cnt !=expects)begin $display("At time %t cnt is %b and should be %b", $time,cnt,expects); $display("TEST FAILED"); $finish; endendtaskinitial begin (

8、negedge clk) rst_,load,data=7'b0_X_XXXXX;(negedge clk)expect(5'h00); rst_,load,data=7'b1_1_11101;(negedge clk)expect(5'h1D); rst_,load,data=7'b1_0_11101; repeat(5)(negedge clk); expect(5'h02); rst_,load,data=7'b1_1_11111;(negedge clk)expect(5'h1F); rst_,load,data=7

9、9;b0_X_XXXXX;(negedge clk)expect(5'h00); $display("TEST PASSED"); $finish; endendmodule四、 仿真結(jié)果與波形五、 思考題該電路中，rst-是同步還是異步清零端？在counter.v的always塊中reset沒(méi)有等時(shí)鐘，而是直接清零。所以是異步清零端。LAB 3：簡(jiǎn)單時(shí)序邏輯電路的設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康氖褂妙A(yù)定義的庫(kù)元件來(lái)設(shè)計(jì)八位寄存器。二、 實(shí)驗(yàn)原理八位寄存器中，每一位寄存器由一個(gè)二選一MUX和一個(gè)觸發(fā)器dffr組成，當(dāng)load=1，裝載數(shù)據(jù)；當(dāng)load=0，寄存器保持。對(duì)于處理重復(fù)

10、的電路，可用數(shù)組條用的方式，使電路描述清晰、簡(jiǎn)潔。三、 源代碼clock.vtimescale 1 ns /1 nsmodule clock(clk);reg clk;output clk;initial beginclk=0;forever begin#10 clk=1'b1;#10 clk=1'b0;endendendmodulemux及dffr模塊調(diào)用代碼mux mux7(.out(n17),.sel(load),.b(data7),.a(out7);dffr dffr7(.q(out7), .d(n17), .clk(clk), .rst_(rst_);mux mux6

11、(.out(n16),.sel(load),.b(data6),.a(out6);dffr dffr6(.q(out6), .d(n16), .clk(clk), .rst_(rst_);mux mux5(.out(n15),.sel(load),.b(data5),.a(out5);dffr dffr5(.q(out5), .d(n15), .clk(clk), .rst_(rst_);mux mux4(.out(n14),.sel(load),.b(data4),.a(out4);dffr dffr4(.q(out4), .d(n14), .clk(clk), .rst_(rst_);mu

12、x mux3(.out(n13),.sel(load),.b(data3),.a(out3);dffr dffr3(.q(out3), .d(n13), .clk(clk), .rst_(rst_);mux mux2(.out(n12),.sel(load),.b(data2),.a(out2);dffr dffr2(.q(out2), .d(n12), .clk(clk), .rst_(rst_);mux mux1(.out(n11),.sel(load),.b(data1),.a(out1);dffr dffr1(.q(out1), .d(n11), .clk(clk), .rst_(rs

13、t_);mux mux0(.out(n10),.sel(load),.b(data0),.a(out0);dffr dffr0(.q(out0), .d(n10), .clk(clk), .rst_(rst_);例化寄存器register r1(.data(data),.out(out),.load(load),.clk(clk),.rst_(rst_);例化時(shí)鐘clock c1(.clk(clk);添加檢測(cè)信號(hào)initialbegin$timeformat(-9,1,"ns",9);$monitor("time=%t,clk=%b,data=%h,load=%b

14、,out=%h",$stime,clk,data,load,out);$dumpvars(2,register_test);end四、 仿真結(jié)果與波形LAB 4：用always塊實(shí)現(xiàn)較復(fù)雜的組合邏輯電路一、 實(shí)驗(yàn)?zāi)康恼莆沼胊lways實(shí)現(xiàn)組合邏輯電路的方法；了解assign與always兩種組合邏輯電路實(shí)現(xiàn)方法之間的區(qū)別。二、 實(shí)驗(yàn)原理僅使用assign結(jié)構(gòu)來(lái)實(shí)現(xiàn)組合邏輯電路，在設(shè)計(jì)中會(huì)發(fā)現(xiàn)很多地方顯得冗長(zhǎng)且效率低下。適當(dāng)?shù)厥褂胊lways來(lái)設(shè)計(jì)組合邏輯，會(huì)更具實(shí)效。本實(shí)驗(yàn)描述的是一個(gè)簡(jiǎn)單的ALU指令譯碼電路的設(shè)計(jì)示例。它通過(guò)對(duì)指令的判斷，對(duì)輸入數(shù)據(jù)執(zhí)行相應(yīng)的操作，包括加、減、或和傳

15、數(shù)據(jù)，并且無(wú)論是指令作用的數(shù)據(jù)還是指令本身發(fā)生變化，結(jié)果都要做出及時(shí)的反應(yīng)。示例中使用了電平敏感的always塊，電平敏感的觸發(fā)條件是指在后括號(hào)內(nèi)電平列表的任何一個(gè)電平發(fā)生變化就能觸發(fā)always塊的動(dòng)作，并且運(yùn)用了case結(jié)構(gòu)來(lái)進(jìn)行分支判斷。在always中適當(dāng)運(yùn)用default（在case結(jié)構(gòu)中）和else（子ifelse結(jié)構(gòu)中），通?？梢跃C合為純組合邏輯，盡管被賦值的變量一定要定義為reg型。如果不使用default或else對(duì)缺省項(xiàng)進(jìn)行說(shuō)明，易產(chǎn)生意想不到的鎖存器。三、 源代碼電路描述always(opcode or data or accum)beginif(accum=8'

16、b00000000)#1.2 zero=1;else#1.2 zero=0;case(opcode)PASS0: #3.5 out =accum;PASS1: #3.5 out =accum;ADD: #3.5 out = data + accum;AND: #3.5 out =data&accum;XOR: #3.5 out =dataaccum;PASSD: #3.5 out=data;PASS6:#3.5 out=accum;PASS7:#3.5 out=accum;default:#3.5 out=8'bx;endcaseend四、 仿真結(jié)果與波形LAB 5：存儲(chǔ)器電路

17、的設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康脑O(shè)計(jì)和測(cè)試存儲(chǔ)器電路。二、 實(shí)驗(yàn)原理本實(shí)驗(yàn)中，設(shè)計(jì)一個(gè)模塊名為mem的存儲(chǔ)器仿真模型，該存儲(chǔ)器具有雙線數(shù)據(jù)總線及異步處理功能。由于數(shù)據(jù)是雙向的，所以要注意，對(duì)memory的讀寫在時(shí)序上要錯(cuò)開(kāi)。三、 源代碼自行添加的代碼assign data= (read)?memoryaddr:8'hZ;always (posedge write)beginmemoryaddr<=data7:0;end四、 仿真結(jié)果與波形LAB 6：設(shè)計(jì)時(shí)序邏輯時(shí)采用阻塞賦值與非阻塞賦值的區(qū)別一、 實(shí)驗(yàn)?zāi)康拿鞔_掌握阻塞賦值與非阻塞賦值的概念和區(qū)別；了解阻塞賦值的使用情況。二、 實(shí)驗(yàn)原理在al

18、ways塊中，阻塞賦值可以理解為賦值語(yǔ)句是順序執(zhí)行的，而非阻塞賦值可以理解為并發(fā)執(zhí)行的。實(shí)際時(shí)序邏輯設(shè)計(jì)中，一般情況下非阻塞賦值語(yǔ)句被更多的使用，有時(shí)為了在同一周期實(shí)現(xiàn)相互關(guān)聯(lián)的操作，也使用阻塞賦值語(yǔ)句。三、 源代碼blocking.vtimescale 1 ns/ 100 psmodule blocking(clk,a,b,c); output3:0b,c; input 3:0a; input clk; reg 3:0b,c; always(posedge clk) begin b =a; c =b; $display("Blocking: a=%d,b=%d,c=%d."

19、;,a,b,c); endendmodulenon_blocking.vtimescale 1 ns/ 100 psmodule non_blocking(clk,a,b,c);output3:0 b,c;input3:0 a;input clk;reg 3:0b,c;always (posedge clk)beginb<=a;c<=b;$display("Non_blocking:a=%d,b=%d,c=%d",a,b,c);endendmodulecompareTop.vtimescale 1 ns/ 100 psmodule compareTop;wire

20、 3:0 b1,c1,b2,c2;reg3:0a;reg clk;initialbeginclk=0;forever #50 clk=clk;endinitial$dumpvars (2,compareTop);initialbegina=4'h3;$display("_");# 100 a =4'h7;$display("_");# 100 a =4'hf;$display("_");# 100 a =4'ha;$display("_");# 100 a =4'h2;$di

21、splay("_");# 100 $display("_");$finish;endnon_blocking nonblocking(clk,a,b2,c2);blocking blocking(clk,a,b1,c1);endmodule四、 仿真結(jié)果與波形LAB 7：利用有限狀態(tài)機(jī)進(jìn)行復(fù)雜時(shí)序邏輯的設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康恼莆绽糜邢逘顟B(tài)機(jī)(FSM)實(shí)現(xiàn)復(fù)雜時(shí)序邏輯的方法。二、 實(shí)驗(yàn)原理控制器是CPU的控制核心，用于產(chǎn)生一系列的控制信號(hào)，啟動(dòng)或停止某些部件。CPU何時(shí)進(jìn)行讀指令，何時(shí)進(jìn)行RAM和I/O端口的讀寫操作等，都由控制器來(lái)控制。三、 源代碼補(bǔ)充代碼

22、nexstate<=state+1'h01;case(state)1:begin sel=1;rd=0;ld_ir=0;inc_pc=0;halt=0;ld_pc=0;data_e=0;ld_ac=0;wr=0;end2:begin sel=1;rd=1;ld_ir=0;inc_pc=0;halt=0;ld_pc=0;data_e=0;ld_ac=0;wr=0;end3:begin sel=1;rd=1;ld_ir=1;inc_pc=0;halt=0;ld_pc=0;data_e=0;ld_ac=0;wr=0;end4:begin sel=1;rd=1;ld_ir=1;inc_p

23、c=0;halt=0;ld_pc=0;data_e=0;ld_ac=0;wr=0;end5:begin sel=0;rd=0;ld_ir=0;inc_pc=1;ld_pc=0;data_e=0;ld_ac=0;wr=0;if(opcode=HLT)halt=1;end6:begin sel=0;rd=alu_op;ld_ir=0;inc_pc=0;halt=0;ld_pc=0;data_e=0;ld_ac=0;wr=0;end7:begin sel=0;rd=alu_op;ld_ir=0;halt=0;data_e=!alu_op;ld_ac=0;wr=0;if(opcode=SKZ)inc_

24、pc<=zero;if(opcode=JMP)ld_pc=1;end0:begin sel=0;rd=alu_op;ld_ir=0;halt=0;data_e=!alu_op;ld_ac=alu_op;inc_pc=(opcode=SKZ)&zero|(opcode=JMP);if(opcode=JMP)ld_pc=1;if(opcode=STO)wr=1;end/default:begin sel=1'bZ;rd=1'bZ;ld_ir=1'bZ;inc_pc=1'bZ;halt=1'bZ;ld_pc=1'bZ;data_e=1&#

25、39;bZ;ld_ac=1'bZ;wr=1'bZ;endendcaseendcontrol_test.v/* * TEST BENCH FOR CONTROLLER * */timescale 1 ns / 1 nsmodule control_test ; reg 8:0 response 0:127; reg 3:0 stimulus 0:15; reg 2:0 opcode; reg clk; reg rst_; reg zero; integer i,j; reg(3*8):1 mnemonic;/ Instantiate controller control c1(r

26、d,wr,ld_ir,ld_ac,ld_pc,inc_pc,halt,data_e,sel,opcode,zero,clk,rst_);/ Define clock initial begin clk = 1 ; forever begin #10 clk = 0 ; #10 clk = 1 ; end end/ Generate mnemonic for debugging purposes always ( opcode ) begin case ( opcode ) 3'h0 : mnemonic = "HLT" ; 3'h1 : mnemonic =

27、 "SKZ" ; 3'h2 : mnemonic = "ADD" ; 3'h3 : mnemonic = "AND" ; 3'h4 : mnemonic = "XOR" ; 3'h5 : mnemonic = "LDA" ; 3'h6 : mnemonic = "STO" ; 3'h7 : mnemonic = "JMP" ; default : mnemonic = "?" ; endc

28、ase end/ Monitor signals initial begin $timeformat ( -9, 1, " ns", 9 ) ; $display ( " time rd wr ld_ir ld_ac ld_pc inc_pc halt data_e sel opcode zero state" ) ; $display ( "- - - - - - - - - - - - -" ) ;/ $shm_open ( "waves.shm" ) ;/ $shm_probe ( "A"

29、 ) ;/ $shm_probe ( c1.state ) ; end/ Apply stimulus initial begin $readmemb ( "stimulus.pat", stimulus ) ; rst_=1; ( negedge clk ) rst_ = 0 ; ( negedge clk ) rst_ = 1 ; for ( i=0; i<=15; i=i+1 ) ( posedge ld_ir ) ( negedge clk ) opcode, zero = stimulusi ; end/ Check response initial beg

30、in $readmemb ( "response.pat", response ) ; ( posedge rst_ ) for ( j=0; j<=127; j=j+1 ) ( negedge clk ) begin $display("%t %b %b %b %b %b %b %b %b %b %b %b %b", $time,rd,wr,ld_ir,ld_ac,ld_pc,inc_pc,halt,data_e,sel,opcode,zero,c1.state ) ; if ( rd,wr,ld_ir,ld_ac,ld_pc,inc_pc,ha

31、lt,data_e,sel != responsej ) begin : blk reg 8:0 r; r = responsej; $display ( "ERROR - response should be:" ) ; $display ( "%t %b %b %b %b %b %b %b %b %b", $time,r8,r7,r6,r5,r4,r3,r2,r1,r0 ) ; $display ( "TEST FAILED" ) ;$stop; $finish ; end end $display ( "TEST PA

32、SSED" ) ; $stop; $finish ; endendmodule四、 仿真結(jié)果與波形LAB 8：通過(guò)模塊間的調(diào)用實(shí)現(xiàn)自頂向下CPU的是設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康膶W(xué)習(xí)和使用層次化、結(jié)構(gòu)化設(shè)計(jì)方法。二、 實(shí)驗(yàn)原理Verilog HDL中，上層模塊引用下層模塊與C語(yǔ)言中程序調(diào)用有些類似，被引用的子模塊在綜合時(shí)作為其父模塊的一部分被綜合，形成相應(yīng)的電路結(jié)構(gòu)。在進(jìn)行模塊實(shí)例引用時(shí)，必須注意的是模塊之間對(duì)應(yīng)的端口，即子模塊端口與父模塊的內(nèi)部信號(hào)必須是一一對(duì)應(yīng)。三、 源代碼CPUtest1.dat/opcode_operand / addr assembly code/- / - -00 1

33、11_11110 / 00 BEGIN: JMP TST_JMP 000_00000 / 01 HLT /JMP did not work at all 000_00000 / 02 HLT /JMP did not load PC, it skipped 101_11010 / 03 JMP_OK: LDA DATA_1 001_00000 / 04 SKZ 000_00000 / 05 HLT /SKZ or LDA did not work 101_11011 / 06 LDA DATA_2 001_00000 / 07 SKZ 111_01010 / 08 JMP SKZ_OK 000

34、_00000 / 09 HLT /SKZ or LDA did not work 110_11100 / 0A SKZ_OK: STO TEMP /store non-zero value in TEMP 101_11010 / 0B LDA DATA_1 110_11100 / 0C STO TEMP /store zero value in TEMP 101_11100 / 0D LDA TEMP 001_00000 / 0E SKZ /check to see if STO worked 000_00000 / 0F HLT /STO did not work 100_11011 / 1

35、0 XOR DATA_2 001_00000 / 11 SKZ /check to see if XOR worked 111_10100 / 12 JMP XOR_OK 000_00000 / 13 HLT /XOR did not work at all 100_11011 / 14 XOR_OK: XOR DATA_2 001_00000 / 15 SKZ 000_00000 / 16 HLT /XOR did not switch all bits 000_00000 / 17 END: HLT /CONGRATULATIONS - TEST1 PASSED! 111_00000 /

36、18 JMP BEGIN /run test again1A 00000000 / 1A DATA_1: /constant 00(hex) 11111111 / 1B DATA_2: /constant FF(hex) 10101010 / 1C TEMP: /variable - inititially AA(hex)1E 111_00011 / 1E TST_JMP: JMP JMP_OK000_00000 / 1F HLT /JMP is brokenCPUtest2.dat/opcode_operand / addr assembly code/- / - -00 101_11011

37、 / 00 BEGIN: LDA DATA_2 011_11100 / 01 AND DATA_3 100_11011 / 02 XOR DATA_2 001_00000 / 03 SKZ 000_00000 / 04 HLT /AND doesn't work 010_11010 / 05 ADD DATA_1 001_00000 / 06 SKZ 111_01001 / 07 JMP ADD_OK 000_00000 / 08 HLT /ADD doesn't work 100_11100 / 09 XOR DATA_3 010_11010 / 0A ADD DATA_1

38、/FF plus 1 makes -1 110_11101 / 0B STO TEMP 101_11010 / 0C LDA DATA_1 010_11101 / 0D ADD TEMP /-1 plus 1 should make zero 001_00000 / 0E SKZ 000_00000 / 0F HLT /ADD Doesn't work 000_00000 / 10 END: HLT /CONGRATULATIONS - TEST2 PASSED! 111_00000 / 11 JMP BEGIN /run test again1A 00000001 / 1A DATA

39、_1: /constant 1(hex) 10101010 / 1B DATA_2: /constant AA(hex) 11111111 / 1C DATA_3: /constant FF(hex) 00000000 / 1D TEMP:CPUtest3.dat/opcode_operand / addr assembly code/- / - - 111_00011 / 00 JMP LOOP /jump to the address of LOOP03 101_11011 / 03 LOOP: LDA FN2 /load value in FN2 into accum 110_11100

40、 / 04 STO TEMP /store accumulator in TEMP 010_11010 / 05 ADD FN1 /add value in FN1 to accumulator 110_11011 / 06 STO FN2 /store result in FN2 101_11100 / 07 LDA TEMP /load TEMP into the accumulator 110_11010 / 08 STO FN1 /store accumulator in FN1 100_11101 / 09 XOR LIMIT /compare accumulator to LIMI

41、T 001_00000 / 0A SKZ /if accum = 0, skip to DONE 111_00011 / 0B JMP LOOP /jump to address of LOOP 000_00000 / 0C DONE: HLT /end of program 101_11111 / 0D AGAIN: LDA ONE 110_11010 / 0E STO FN1 101_11110 / 0F LDA ZERO 110_11011 / 10 STO FN2 111_00011 / 11 JMP LOOP /jump to address of LOOP1A 00000001 /

42、 1A FN1: /variable - stores 1st Fib. No. 00000000 / 1B FN2: /variable - stores 2nd Fib. No. 00000000 / 1C TEMP: /temporary variable 10010000 / 1D LIMIT: /constant 144 - max value 00000000 / 1E ZERO: /constant 0 00000001 / 1F ONE: /constant 1CPUtest4.dat 自己編寫的CPUtest，實(shí)現(xiàn)乘法器/opcode_operand / addr assem

43、bly code/- / - -03 111_00100 / 03 JMP LOOP /jump to the address of LOOP 101_11011 / 04 LOOP: LDA DATA2 /A=5 010_11010 / 05 ADD DATA1 /A=5+5=10 110_11011 / 06 STO DATA2 /DATA2=10 101_11101 / 07 LDA TIME /A=TIME 011_11111 / 08 AND TIME /A =TIME 010_11100 / O9 ADD TEMP /A=TIME+1 110_11101 / 0A STO TIME /TIME=TIME+1 100_11110 / 0B XOR LIMIT /compare accumulator to LIMIT 001_00000 / 0C SKZ /if accum = 0, skip to DONE 111_00100 / 0D JMP LOOP /jump to a