VHDL數(shù)字秒表設(shè)計(jì)

1、VHDL數(shù)字秒表設(shè)計(jì) 專 業(yè)： 自動(dòng)化 班級(jí)學(xué)號(hào)： 5090629 姓 名： 劉丹 2011年 6 月14 日VHDL語言課程設(shè)計(jì)-秒表設(shè)計(jì)一、設(shè)計(jì)實(shí)驗(yàn)?zāi)康模涸贛AX+plusII軟件平臺(tái)上，熟練運(yùn)用VHDL語言，完成數(shù)字時(shí)鐘設(shè)計(jì)的軟件編程、編譯、綜合、仿真，使用EDA實(shí)驗(yàn)箱，實(shí)現(xiàn)數(shù)字秒表的硬件功能。二、設(shè)計(jì)實(shí)驗(yàn)說明及要求：1、數(shù)字秒表主要由：分頻器、掃描顯示譯碼器、一百進(jìn)制計(jì)數(shù)器、六十進(jìn)制計(jì)數(shù)器（或十進(jìn)制計(jì)數(shù)器與6進(jìn)制計(jì)數(shù)器）、十二進(jìn)制計(jì)數(shù)器（或二十四進(jìn)制計(jì)數(shù)器）電路組成。在整個(gè)秒表中最關(guān)鍵的是如何獲得一個(gè)精確的100HZ計(jì)時(shí)脈沖，除此之外，數(shù)字秒表需有清零控制端，以及啟動(dòng)控制端、保持保持，

2、以便數(shù)字時(shí)鐘能隨意停止及啟動(dòng)。2、數(shù)字秒表顯示由時(shí)（12或24進(jìn)制任選）、分（60進(jìn)制）、秒（60進(jìn)制）、百分之一秒（一百進(jìn)制）組成，利用掃描顯示譯碼電路在八個(gè)數(shù)碼管顯示。3、能夠完成清零、啟動(dòng)、保持（可以使用鍵盤或撥碼開關(guān)置數(shù)）功能。4、時(shí)、分、秒、百分之一秒顯示準(zhǔn)確。三、我的設(shè)計(jì)思路：    1、四個(gè)十進(jìn)制計(jì)數(shù)器：用來分別對(duì)百分之一秒、十分之秒、秒和分進(jìn)行計(jì)數(shù)；    2、兩個(gè)6進(jìn)制計(jì)數(shù)器：用來分別對(duì)十秒和十分進(jìn)行計(jì)數(shù)；3、一個(gè)24進(jìn)制計(jì)數(shù)器，用來對(duì)小時(shí)進(jìn)行計(jì)數(shù)；    3、分頻率器：用來產(chǎn)生100H

3、z的計(jì)數(shù)脈沖；    4、顯示譯碼器：完成對(duì)顯示譯碼的控制。四、設(shè)計(jì)過程：1.分頻器：由10MHz變?yōu)?00Hz，10MHz的周期是10的（-7）次方，而100Hz的周期是10的（-2）次方，而且方波是高低相間，只有高電平有效，所以100Hz的周期需要取一半，即0.02秒，這樣算出的分頻倍數(shù)就是50000分頻器代碼：將10MHz脈沖變成100Hz程序：library ieee;use ieee.std_logic_1164.all;entity fenpin is port(clr,clk: in bit;q: buffer bit);end fenpi

4、n;architecture a of fenpin is   signal counter:integer range 0 to 49999;begin    process(clr,clk)      begin  if (clk='1' and clk'event) then         if clr='1' then  

5、60;         counter<=0;  elsif counter=49999 then            counter<=0;            q<= not q;    else 

6、60;          counter<=counter+1;         end if;       end if;     end process；end a;分頻器的仿真圖：2.十進(jìn)制計(jì)數(shù)器：原理為加法計(jì)數(shù)器，從0加到9，計(jì)到10個(gè)數(shù)時(shí)由cout進(jìn)位程序：library ieee; use ieee.std_l

7、ogic_1164.all;use ieee.std_logic_unsigned.all;entity c10 is    port(clr,start,clk: in bit;      cout: out bit;      daout: out std_logic_vector(3 downto 0);end c10;,architecture a of c10 is    signal temp:std_l

8、ogic_vector(3 downto 0);begindaout<=temp;    process(clk,clr)    begin        if clr='1' then                temp<="0000" 

9、0;             cout<='0'         elsif (clk'event and clk='1') then               if start='1' then 

10、0;          if temp>="1001" then                 temp<="0000"              

11、;   cout<='1'                  else                     temp<=temp+1;    

12、60;                 cout<='0'                  end if;             &#

13、160;  end if;         end if;          end process;end a;十進(jìn)制計(jì)數(shù)器仿真圖：3.六進(jìn)制計(jì)數(shù)器：原理為加法計(jì)數(shù)器，從0 加到5計(jì)到第六個(gè)數(shù)時(shí)由cout進(jìn)位。程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity c6 is    port(cl

14、r,start,clk: in bit;         daout: out std_logic_vector(3 downto 0);         cout: out std_logic);end c6;architecture a of c6 is    signal temp:std_logic_vector(3 downto 0);begindaout<=temp;  

15、;  process(clk,clr)    begin       if clr='1' then              temp<="0000"             cout<='0'

16、        elsif (clk'event and clk='1') then       if start='1' then        if temp>="0101" then             

17、      temp<="0000"                  cout<='1'                 else   &#

18、160;                temp<=temp+1;                     cout<='0'         

19、;        end if;               end if;        end if; end process; end a;6進(jìn)制計(jì)數(shù)器仿真圖：4、二十四進(jìn)制計(jì)數(shù)器采用一個(gè)二進(jìn)制的計(jì)數(shù)器和一個(gè)四進(jìn)制的計(jì)數(shù)器相結(jié)合到一起，低位從0到9，到9向高位進(jìn)一，當(dāng)?shù)臀挥?jì)到四，高位計(jì)到2，進(jìn)行進(jìn)位輸出，即每二十四個(gè)數(shù)進(jìn)行一次進(jìn)位輸

20、出library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity c24 isport(clr,start,clk:in std_logic;hour1,hour0:out std_logic_vector(3 downto 0);end c24;architecture a of c24 isbegin process(clr,clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clr='1' then cnt0:

21、="0000" cnt1:="0000"elsif clk'event and clk='1' thenif start='1' thenif cnt1="0010" and cnt0="0011"then cnt1:="0000"cnt0:="0000"elsif cnt0<"1001" then cnt0:=cnt0+1;else cnt0:="0000"cnt1:=cnt1+1;end

22、 if;end if;end if;hour1<=cnt1;hour0<=cnt0;end process;end a;24進(jìn)制計(jì)數(shù)器仿真圖：5.數(shù)據(jù)選擇和數(shù)碼管選擇模塊代碼：其功能是選擇計(jì)數(shù)端口來的數(shù)據(jù)，當(dāng)相應(yīng)的數(shù)據(jù)到來時(shí)數(shù)據(jù)選擇器數(shù)據(jù)后輸數(shù)給數(shù)碼管，并由數(shù)碼管顯示。八個(gè)數(shù)碼管分別顯示小時(shí)，分鐘，秒，百分秒library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity seltime isport(clk: in bit;dain0,dain1,dain2,dain3,dain4,da

23、in5,dain6,dain7: in std_logic_vector(3 downto 0);sel: out std_logic_vector(2 downto 0);daout: out std_logic_vector(3 downto 0);end seltime;architecture a of seltime issignal temp:integer range 0 to 7;beginprocess(clk)beginif (clk='1'and clk'event) thenif temp=7 then temp<=0;else temp&

24、lt;=temp + 1;end if;case temp iswhen 0=>sel<="000"daout<=dain0;when 1=>sel<="001"daout<=dain1;when 2=>sel<="010"daout<=dain2;when 3=>sel<="011"daout<=dain3;when 4=>sel<="100"daout<=dain4;when 5=>sel<

25、="101"daout<=dain5;when 6=>sel<="110"daout<=dain6;when 7=>sel<="111"daout<=dain7;end case;end if;end process;end a;仿真圖：5.數(shù)碼管驅(qū)動(dòng)模塊代碼：數(shù)碼管驅(qū)動(dòng)電路，驅(qū)動(dòng)數(shù)碼管發(fā)光。library ieee;use ieee.std_logic_1164.all;entity deled isport(num:in std_logic_vector(3 downto 0);led:out std_logic_vector(6 downto 0);end deled ;architecture a of deled isbeginprocess(num)begincase num iswhen"0000"=>led<="0111111"-3FHwhen"0001"=>led<="0000110"-06Hwhen"0010&quo