




版權(quán)說明:本文檔由用戶提供并上傳,收益歸屬內(nèi)容提供方,若內(nèi)容存在侵權(quán),請進(jìn)行舉報或認(rèn)領(lǐng)
文檔簡介
1、/* NCO/* LIBRARY lpm;LIBRARY ieee;Entity nco ISGENERIC(WIDTH :INTEGER:=28;PORT(fcw :IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0; sin,cos,acc :OUT STD_LOGIC_VECTOR(7 DOWNTO 0; clk :IN STD_LOGIC;END nco;Architecture rtl OF nco ISSIGNAL s,acc28: STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0; SIGNAL msbs : STD_LOGIC_VECTO
2、R(7 DOWNTO 0;SIGNAL sin_cos: STD_LOGIC_VECTOR(15 DOWNTO 0;BEGINadd1:lpm_add_subGENERIC MAP(LPM_WIDTH=>WIDTH,LPM_REPRESENTATION=>"SIGNED",LPM_DIRECTION=>"ADD",LPM_PIPELINE=>0PORT MAP(dataa=>fcw,datab=>acc28,result=>s;reg1:lpm_ffGENERIC MAP(LPM_WIDTH=>WIDTHP
3、ORT MAP(data=>s,q=>acc28,clock=>clk;select1:PROCESS(acc28V ARIABLE i:INTEGER;BEGINFOR i IN 7 DOWNTO 0 LOOPmsbs(i<=acc28(27-7+i;END LOOP;END PROCESS select1;acc<=msbs;rom1:lpm_romGENERIC MAP(LPM_WIDTH=>16,LPM_WIDTHAD=>8,PORT MAP(address=>msbs,inclock=>clk,outclock=>clk,q
4、=>sin_cos;select2:PROCESS(sin_cosV ARIABLE i:INTEGER;BEGINFOR i IN 7 DOWNTO 0 LOOPcos(i<=sin_cos (15-7+i;sin(i <=sin_cos (i;END LOOP;END PROCESS select2;END rtl;/* NCO+MIXER/* LIBRARY lpm;LIBRARY ieee;Entity system ISGENERIC(WIDTHA :INTEGER:=12;WIDTHB :INTEGER:=8;WIDTHP :INTEGER:=20;PORT(cl
5、ock :IN STD_LOGIC;ADout :IN STD_LOGIC_VECTOR(11 DOWNTO 0;Phase_in :IN STD_LOGIC_VECTOR(27 DOWNTO 0;datai,dataq :OUT STD_LOGIC_VECTOR(19 DOWNTO 0 ;END system;Architecture rtl OF system ISCOMPONENT ncoPORT(fcw :IN STD_LOGIC_VECTOR(27 DOWNTO 0; sin,cos,acc :OUT STD_LOGIC_VECTOR(7 DOWNTO 0;clk :IN STD_L
6、OGIC;END COMPONENT;SIGNAL cosout,sinout: STD_LOGIC_VECTOR(7 DOWNTO 0;SIGNAL mixer_i,mixer_q: STD_LOGIC_VECTOR(19 DOWNTO 0; BEGINu0:nco PORT MAP(fcw=>Phase_in,clk=>clock,sin=>sinout,cos=>cosout; mul1:lpm_multLPM_WIDTHB=>WIDTHB,LPM_WIDTHP=>WIDTHP,LPM_WIDTHS=>WIDTHP,LPM_REPRESENTAT
7、ION=>"SIGNED"PORT MAP(dataa=>ADout,datab=>cosout,result=>mixer_i;mul2:lpm_multGENERIC MAP(LPM_WIDTHA=>WIDTHA,LPM_WIDTHB=>WIDTHB,LPM_WIDTHP=>WIDTHP,LPM_WIDTHS=>WIDTHP,LPM_REPRESENTATION=>"SIGNED"PORT MAP(dataa=>ADout,datab=>sinout,result=>mixer_
8、q;PROCESS(clockBEGINdatai<=mixer_i;dataq<=mixer_q;End PROCESS;/*GAIN ADJUSTING/*library ieee;entity shiftadj isport(Din :in std_logic_vector(11 downto 0;SG1 :in std_logic_vector(1 downto 0;Dout:out std_logic_vector(11 downto 0;end shiftadj;architecture shift_arch of shiftadj isbeginprocess(Din
9、variable shiftB: std_logic_vector(1 downto 0;variable signbit: std_logic;beginshiftB:=SG1;signbit:=Din(Din'high;case shiftB iswhen "00"=> Dout<=signbit&signbit&Din(11 downto 2;when "01"=> Dout<=signbit&signbit&signbit&signbit&Din(11when&quo
10、t;10"=>Dout<=signbit&signbit&signbit&signbit&signbit&signbit&signbit&signbit&Din(11 downto 8;whenothers=>Dout<=signbit&signbit&signbit&signbit&signbit&signbit&signbit&signbit&signbit&signbit&signbit&si gnbit
11、;end case;end process;end shift_arch;END rtl;/* CIC-DIVIDE_M/* library ieee;entity divm isport (clk:in std_logic;M:in std_logic_vector(3 downto 0;q:out std_logic;end divm;architecture rtl of divm issignal ca:std_logic;beginprocess(clkvariable qm:integer;beginif(clk'EVENT AND clk='1'theni
12、f(qm=CONV_INTEGER(Mthenqm:=0;ca<='0'elsif(qm=CONV_INTEGER(M-1thenca<='1'qm:=qm+1;elseqm:=qm+1;ca<='0'end if;end if;q<=ca;end process;/* CIC-DECIMATER (M=216/* PACKAGE n_bit_int ISSUBTYPE word28 IS INTEGER RANGE 0 TO 2*28-1;END n_bit_int;LIBRARY work;LIBRARY ieee;E
13、NTITY cic4secdec ISPORT ( clk : IN STD_LOGIC;x_in: IN STD_LOGIC_VECTOR(11 DOWNTO 0;div_M:IN STD_LOGIC_VECTOR(3 DOWNTO 0;y_out:OUT STD_LOGIC_VECTOR(11 DOWNTO 0;END cic4secdec;ARCHITECTURE flex OF cic4secdec IScomponent divmport (clk:in std_logic;M:in std_logic_vector(3 downto 0;q:out std_logic;end co
14、mponent;SIGNAL clk2 : STD_LOGIC;SIGNAL x : STD_LOGIC_VECTOR(11 DOWNTO 0;SIGNAL sxtx : STD_LOGIC_VECTOR(27 DOWNTO 0;SIGNAL i0, i1 , i2,i3 : word28;SIGNAL i2d1, c1, c0 : word28;SIGNAL c1d1,c2d1, c3d1, c2 , c3,c4: word28;BEGINu0:divm PORT MAP(clk=>clk,M=>div_M,q=>clk2;sxt: PROCESS (xBEGINsxtx(
15、11 DOWNTO 0 <= x;FOR k IN 27 DOWNTO 12 LOOPsxtx(k <=x(x'high;END LOOP;END PROCESS sxt;Int: PROCESSWAIT UNTIL clk = '1'x <= x_in;i0 <= i0 + CONV_INTEGER(sxtx;i1 <= i1 + i0;i2 <= i2 + i1;i3 <= i3 + i2;end PROCESS Int;Comb: PROCESSBEGINWAIT UNTIL clk2 = '1'c0<
16、;=i3;i2d1 <= c0;c1 <=c0-i2d1;c1d1 <=c1;c2 <=c1-c1d1;c2d1 <=c2;c3 <=c2-c2d1;c3d1 <=c3;c4 <=c3-c3d1;END PROCESS Comb;y_out<= CONV_STD_LOGIC_VECTOR(c4/2*16,12;END flex;/* FIR-filter_state controlling/* LIBRARY ieee;ENTITY controller2 ISPORT(CLK: IN STD_LOGIC;clear :OUT STD_LO
17、GIC;plsr_load: OUT STD_LOGIC;add_sub_S1 :OUT STD_LOGIC;add_sub_S2 : OUT STD_LOGIC;END controller2;ARCHITECTURE controller_state OF controller2 ISTYPE STATE_TYPE IS (S1,S2,S3;SIGNAL state: STATE_TYPE;BEGINstate_logic: processvariable count :integer range 0 to 8;beginwait until CLK ='1' ;case
18、state iswhen S1=> clear<='1'plsr_load<='1'add_sub_S1<='0'add_sub_S2<='1'state<=S2;count:=0;when S2=> clear<='1' ;plsr_load<='1'add_sub_S1 <='0'add_sub_S2<='0'if(count=6thenstate<=S3;elsestate <=S2;
19、count:=count+1;end if;when S3=> clear<='0'plsr_load<='0'add_sub_S1<='1'add_sub_S2<='0'state<=S1;end case;end process;END controller_state;/* FIR-Parallel to Serial conversion/* library ieee;entity ptos isport(data: in std_logic_vector(7 downto 0;clk
20、: in std_logic;ptos_load : in std_logic;q:out std_logic;end ptos;ARCHITECTURE rtl OF ptos ISsignal q_temp:std_logic_vector(7 downto 0;beginprocess(clkbeginif(clk'event and clk='1'thenif (ptos_load='0' thenq_temp<=data;elseq_temp<=q_temp(6 downto 0&q_temp(0;end if;end if
21、;q<=q_temp(7;end process;end rtl;/* FIR-shiftregister/*library ieee;entity shiftregister isport(din:in std_logic;cp:in std_logic;dout: OUT std_logic_vector(15 downto 0;end shiftregister;ARCHITECTURE structure OF shiftregister IScomponent shift_regport(d1: in std_logic;cp:in std_logic;d0:OUT std_l
22、ogic;end component;SIGNAL q_temp:std_logic_vector(15 downto 0;BEGINq_temp(0<=din;label2:for i in 0 to 14 generateshift_regx: shift_reg port map (q_temp(i,cp,q_temp(i+1;end generate label2;dout<=q_temp(15 downto 0;END structure;/* FIR-serial_adder/* library ieee;entity isport(A: in std_logic;B:
23、 in std_logic;clk: in std_logic;clr: in std_logic;S: out std_logic;end serial_adder;architecture structure of serial_adder issignal tmp1,tmp2,Cin,Cout:std_logic;beginlable1:process(clk,clrbeginif (clk'event and clk='1'thenif (clr='0'thenCin<='0'else Cin<=Cout;end if
24、;end if;end process;tmp1<=A xor B;tmp2<=tmp1 and Cin;S<=tmp1 xor Cin;Cout<=tmp2 or(A and B;end structure;/* FIR-serial_adder8/* library ieee;entity serial_adder8 isport(A: in std_logic_vector(7 downto 0;B: in std_logic_vector(7 downto 0;clk: in std_logic;clear: in std_logic;S: out std_lo
25、gic_vector(7 downto 0;end serial_adder8;architecture structure of serial_adder8 iscomponent serial_adderport(A: in std_logic;B: in std_logic;clk: in std_logic;clr: in std_logic;S: out std_logic;end component;beginlabel1: for i in 0 to 7 generateserialadderx: serial_adder port map (A(i,B(i,clk,clear,
26、S(i;end generate label1;end structure;/* FIR-coder/* library ieee;entity coder isport(S: in std_logic_vector(7 downto 0;address1:out std_logic_vector(2 downto 0;address2:out std_logic_vector(2 downto 0;end coder;ARCHITECTURE dataflow OF coder ISbeginaddress1(2<= S(7 xor S(6;address1(1<= S(7 xo
27、r S(5;address1(0<= S(7 xor S(4;address2(2<= S(3 xor S(2;address2(1<= S(3 xor S(1;address2(0<= S(3 xor S(0;end dataflow;/* FIR-LUT/* library ieee;entity lut1 isport(table_in:in std_logic_vector(2 downto 0;table_out: out std_logic_vector(8 downto 0;end lut1;architecture lcs1 of lut1 isbegi
28、nprocessbegincase table_in iswhen "000"=>table_out<="111111110"when "001"=>table_out<="000000110"when "010"=>table_out<="111111011"when "011"=>table_out<="000000011"when "100"=>table_
29、out<="111111010"when "101"=>table_out<="000000010"when "110"=>table_out<="111110111"when "111"=>table_out<="111111111"when others=>table_out<="000000000"end case;end process;end lcs1;library ie
30、ee;entity lut2 isport(table_in:in std_logic_vector(2 downto 0;table_out: out std_logic_vector(8 downto 0;end lut2;architecture lcs2 of lut2 isbeginprocessbegincase table_in iswhen "000"=>table_out<="111100010"when "001"=>table_out<="000100001"when
31、"010"=>table_out<="111101110"when "011"=>table_out<="000101101"when "100"=>table_out<="111010011"when "101"=>table_out<="000010010"when "110"=>table_out<="111011111"when
32、"111"=>table_out<="000011110"when others=>table_out<="000000000"end case;end process;end lcs2;/* adder9/* LIBRARY ieee;ENTITY adder9 ISPORT(Cin: IN STD_LOGIC;A,B: IN STD_LOGIC_VECTOR(8 downto 0;S: OUT STD_LOGIC_VECTOR(8 downto 0;END adder9;ARCHITECTURE a OF
33、adder9 ISSIGNAL sA,sB,sS : STD_LOGIC_VECTOR(8 downto 0;SIGNAL sC,sT,sG: STD_LOGIC_VECTOR(8 downto 0;SIGNAL sCin: STD_LOGIC;BEGINsA<= A;sB<= B;sCin <=Cin;sT(0 <= sA(0 xor sB(0;sG(0 <= sA(0 and sB(0;sT(1 <= sA(1 xor sB(1;sG(1 <= sA(1 and sB(1;sT(2 <= sA(2 xor sB(2;sG(2 <= sA
34、(2 and sB(2;sT(3 <= sA(3 xor sB(3;sG(3 <= sA(3 and sB(3;sT(4 <= sA(4 xor sB(4;sG(4 <= sA(4 and sB(4;sT(5 <= sA(5 xor sB(5;sG(5 <= sA(5 and sB(5;sT(6 <= sA(6 xor sB(6;sG(6 <= sA(6 and sB(6;sT(7 <= sA(7 xor sB(7;sT(8 <= sA(8 xor sB(8;sG(8 <= sA(8 and sB(8;sC(0 <= sG
35、(0 or (sT(0 and sCin;sC(1 <= sG(1 or (sT(1 and (sG(0 or (sT(0 and sCin;sC(2 <= sG(2 or (sT(2 and (sG(1 or (sT(1 and (sG(0 or (sT(0 and sCin; sC(3 <= sG(3 or (sT(3 and (sG(2 or (sT(2 and (sG(1 or (sT(1 and (sG(0 or (sT(0 and sCin;sC(4 <= sG(4 or (sT(4 and (sG(3 or (sT(3 and (sG(2 or (sT(2
36、 and (sG(1 or (sT(1 and (sG(0 or (sT(0 and sCin;sC(5 <= sG(5 or (sT(5 and (sG(4 or (sT(4 and (sG(3 or (sT(3 and (sG(2 or (sT(2 and (sG(1 or (sT(1 and (sG(0 or (sT(0 and sCin;sC(6 <= sG(6 or (sT(6 and (sG(5 or (sT(5 and (sG(4 or (sT(4 and (SG(3 or (sT(3 and (sG(2 or (sT(2 and (sG(1 or (sT(1 and
37、 (sG(0 or (sT(0 and sCin;sC(7 <= sG(7 or (sT(7 and (sG(6 or (sT(6 and (sG(5 or (sT(5 and (sG(4 or (sT(4 and (sG(3 or (sT(3 and (sG(2 or (sT(2 and (sG(1 or (sT(1 and (SG(0 or (sT(0and sCin;sC(8 <= sG(8 or (sT(8 and (sG(7 or (sT(7 and (sG(6 or (ST(6 and (sG(5 or (sT(5 and (sG(4 or (sT(4 and (sG(
38、3 or (sT(3 and (sG(2 or (sT(2 and (sG(1 or (sT(1and (sG(0 or (sT(0 and sCin;sS(0 <= sT(0 xor sCin;sS(1 <= sT(1 xor sC(0;sS(2 <= sT(2 xor sC(1;sS(3 <= sT(3 xor sC(2;sS(4 <= sT(4 xor sC(3;sS(5 <= sT(5 xor sC(4;sS(6 <= sT(6 xor sC(5;sS(7 <= sT(7 xor sC(6;sS(8 <= sT(8 xor sC(7
39、;S <= sS;END a;/*mux2/*library ieee;entity mux2 isport(din1:in std_logic_vector(8 downto 0;din2:in std_logic_vector(8 downto 0;s1 :in std_logic;s2 :in std_logic;q_out1:out std_logic_vector(8 downto 0;end mux2;ARCHITECTURE rtl OF mux2 ISsignal d1_1: std_logic_vector(8 downto 0;signal d1_0: std_log
40、ic_vector(8 downto 0;signal d2_1: std_logic_vector(8 downto 0;signal d2_0: std_logic_vector(8 downto 0;BEGINprocess(din1,din2,s1,s2begind1_0<=din1;d1_1<=not(din1;d2_0<=din2;d2_1<=not(din2;case s1 iswhen '0'=>q_out1 <=d1_0;when '1'=>q_out1 <=d1_1;when others=&g
41、t;q_out1<="ZZZZZZZZ"end case;case s2 iswhen '0'=>q_out2 <=d2_0;when '1'=>q_out2 <=d2_1;when others=>q_out2<="ZZZZZZZZ"end case;end process;END rtl;/* FIR- add_sub/* LIBRARY ieee;ENTITY add_sub ISPORT(s7: IN STD_LOGIC;s3: IN STD_LOGIC;add_sub_1
42、 : IN STD_LOGIC;A,B: IN STD_LOGIC_VECTOR(8 downto 0;Cin_b:out std_logic;Sout: OUT STD_LOGIC_VECTOR(8 downto 0;END add_sub;ARCHITECTURE structure OF add_sub IScomponent mux2port(din1 :in std_logic_vector(8 downto 0;din2:in std_logic_vector(8 downto 0;s1 :in std_logic;s2 :in std_logic;q_out2:out std_logic_vector(8 downto 0;end component;component adder9port(Cin: IN STD_LOGIC;A,B: IN STD_LOGIC_VECTOR(8 downto 0;S: OUT STD_LOGIC_VECTOR(8 downto 0;end component;signal contro1_1: STD_LOGIC;signal contro1_2: STD_LOGIC;signal Cin:STD_LOGIC;signal A_1:STD_LOGIC_VECTOR(8 downto 0;signal B
溫馨提示
- 1. 本站所有資源如無特殊說明,都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請下載最新的WinRAR軟件解壓。
- 2. 本站的文檔不包含任何第三方提供的附件圖紙等,如果需要附件,請聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
- 3. 本站RAR壓縮包中若帶圖紙,網(wǎng)頁內(nèi)容里面會有圖紙預(yù)覽,若沒有圖紙預(yù)覽就沒有圖紙。
- 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
- 5. 人人文庫網(wǎng)僅提供信息存儲空間,僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護處理,對用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯,并不能對任何下載內(nèi)容負(fù)責(zé)。
- 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容,請與我們聯(lián)系,我們立即糾正。
- 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時也不承擔(dān)用戶因使用這些下載資源對自己和他人造成任何形式的傷害或損失。
最新文檔
- 2025屆云南省玉溪市峨山縣三中高一物理第二學(xué)期期末聯(lián)考模擬試題含解析
- 建筑單位安全生產(chǎn)許可證
- 社區(qū)對沿街門店安全隱患排查
- 商鋪消防安全檢查記錄表
- 交通運輸標(biāo)準(zhǔn)化管理系統(tǒng)
- ehs智能安全生產(chǎn)管理系統(tǒng)
- 樂山交通事故請律師
- 家具廠安全員崗位職責(zé)
- 2025年廣西壯族自治區(qū)百色市田陽縣田陽高中物理高一下期末教學(xué)質(zhì)量檢測模擬試題含解析
- 教科版必修二 第三章萬有引力定律同步測試題2025屆高二物理第二學(xué)期期末教學(xué)質(zhì)量檢測模擬試題含解析
- 2025年軍人離婚協(xié)議書范本
- 化妝品生產(chǎn)質(zhì)量管理體系手冊
- 娛樂行業(yè):舞蹈演員個人簡介簡歷
- 工程造價復(fù)審報告書范文
- SAP S4HANA 用戶操作手冊-成本控制CO操作手冊-002-訂單成本核算
- 房屋代建協(xié)議書范本
- 幼兒園2025-2026學(xué)年度第一學(xué)期園本培訓(xùn)計劃
- 2025年度礦山開采與沙石資源承包合同范本4篇
- 3D3S基本模塊命令詳解施加荷載地震參數(shù)11課件講解
- 乘聯(lián)會:2024年11月OTA監(jiān)測月報
- 部隊熱射病預(yù)防與急救
評論
0/150
提交評論