LED數(shù)碼管驅(qū)動電路設(shè)計

1、深圳職業(yè)技術(shù)學(xué)院Shenzhen Polytechnic實(shí)訓(xùn)(驗(yàn)報告Training Item編制部門：電信學(xué)院 項(xiàng)目編號Item No.06項(xiàng)目名稱ItemLED數(shù)碼管驅(qū)動電路設(shè)計訓(xùn)練對象Class微電子技術(shù)專業(yè)學(xué)時Time4課程名稱Course可編程邏輯器件應(yīng)用教材TextbookCPLD/FPGA應(yīng)用技術(shù)目 的Objective1.熟練使用Quartus II，掌握整個CPLD/FPGA開發(fā)流程；2.掌握LED數(shù)碼管靜態(tài)顯示的Verilog HDL設(shè)計方法；3掌握LED數(shù)碼管動態(tài)顯示的Verilog HDL設(shè)計方法實(shí)訓(xùn)2 LED數(shù)碼管驅(qū)動電路設(shè)計與實(shí)現(xiàn)一、實(shí)訓(xùn)設(shè)備、工具與要求1實(shí)訓(xùn)設(shè)備、

2、工具PC電腦、FPGA開發(fā)系統(tǒng)、Quartus II應(yīng)用軟件。2實(shí)訓(xùn)要求 每位學(xué)生獨(dú)立完成項(xiàng)目的制作并撰寫實(shí)訓(xùn)報告； 項(xiàng)目制作完成后由制作者按“驗(yàn)收標(biāo)準(zhǔn)”測試功能與參數(shù)，指導(dǎo)教師驗(yàn)收并登記成績； 項(xiàng)目經(jīng)指導(dǎo)教師驗(yàn)收后，由學(xué)生將全部實(shí)驗(yàn)設(shè)備整理后交指導(dǎo)教師驗(yàn)收并登記； 實(shí)訓(xùn)結(jié)束后1周內(nèi)交實(shí)訓(xùn)報告。二、實(shí)訓(xùn)涉及的基本知識1.請畫出七段LED數(shù)碼管顯示電路的輸入輸出結(jié)構(gòu)2.列表描述共陰七段數(shù)碼顯示電路的輸入輸出關(guān)系和顯示結(jié)果？七段數(shù)碼管顯示電路輸入七段數(shù)碼管顯示電路輸出LED顯示字形in3 in2 in1 in0gfedcba0000011111100001000011010010101101120

3、01110011113010011001104010111011015011011111006011100001117100011111118100111001119三、實(shí)訓(xùn)綜合電路（七段譯碼器電路框圖）四、實(shí)訓(xùn)步驟1. 閱讀Altera CyclongII 開發(fā)系統(tǒng)用戶手冊，畫出七段數(shù)碼管的電路圖和連接引腳。信號clkled6led5led4led3led2led1led0rstscan3scan2scan1scan0引腳PIN_W12PIN_W7PIN_AA9PIN_Y9PIN_AB8PIN_AA7PIN_V9PIN_W9PIN_AA3PIN_AB9PIN_AA8PIN_W8PIN_V8值

4、2.設(shè)計應(yīng)用工程，將十進(jìn)制的0-9的BCD碼轉(zhuǎn)換成七段數(shù)碼管的顯示碼（組合邏輯電路）十進(jìn)制數(shù)碼0123456789二進(jìn)制碼0000000100100011010001010110011110001001程序設(shè)計：module qiduan(data_in,data_out;input 3:0 data_in;output 6:0 data_out;reg 6:0 data_out;always(data_inbegincase(cnt4b0000:data_out=7b0111111;4b0001:data_out=7b0000110;4b0010:data_out=7b1011011;4b0

5、011:data_out=7b1001111;4b0100:data_out=7b1100110;4b0101:data_out=7b1101101;4b0110:data_out=7b1111100;4b0111:data_out=7b0000111;4b1000:data_out=7b1111111;4b1001:data_out=7b1100111;default:data_out=7b0000000;endcaseendendmodule3. 設(shè)計應(yīng)用工程，四個數(shù)碼管依次靜態(tài)顯示“1”、“2”、“3”、“4”； module ledjt(rst,scan,led;input rst;o

6、utput 3:0 scan;output6:0 led;reg 3:0 scan;reg6:0 led;reg state;always(rstbeginif(rst=1b0state=2b00;elsestate=state+1;endalways(statebegincase(state2b00:scan=4b0001;2b01:scan=4b0010;2b10:scan=4b0100;2b11:scan=4b1000;endcaseendalways(scanbegincase(scan4b0001:led=7b0000110;4b0010:led=7b1011011;4b0100:l

7、ed=7b1001111;4b1000:led=7b1100110;default:led=7b0111111;endcaseendendmodule4. 設(shè)計應(yīng)用工程，單個數(shù)碼管顯示從模10計數(shù)功能；程序設(shè)計：1、 分頻器模塊module div(clk,rst,clk_1hz;input clk,rst;output clk_1hz;reg clk_1hz;reg 24:0 cnt;always(posedge clk or negedge rstbeginif(rst=1b0begincnt=0;clk_1hz=1b0;endelse if(cnt=25d26214399begincnt

8、=0;clk_1hz=clk_1hz;endelsecnt=cnt+1b1;endendmodule2、 計數(shù)器模塊module cnt10(clk_1hz,cnt,rst;input clk_1hz,rst;output 3:0 cnt;reg 3:0 cnt;always(posedge clk_1hz or negedge rstbeginif(rst=1b0cnt=4b0000;else if(cnt=9cnt=4b0000;else cnt=cnt+1b1;endendmodule功能仿真圖3、 LED譯碼器模塊module qiduan(cnt,data_out;input 3:0

9、 cnt;output 10:0 data_out;reg 10:0 data_out;always(cntbegincase(cnt4b0000:data_out=11b00010111111;4b0001:data_out=11b00010000110;4b0010:data_out=11b00011011011;4b0011:data_out=11b00011001111;4b0100:data_out=11b00011100110;4b0101:data_out=11b00011101101;4b0110:data_out=11b00011111100;4b0111:data_out=

10、11b00010000111;4b1000:data_out=11b00011111111;4b1001:data_out=11b00011100111;default:data_out=11b00000000000;endcaseendendmodule4、頂層模塊module led_1(rst,clk,led;input rst,clk;output 10:0led;wire 10:0led;wire clk_1hz;wire 3:0 cnt;div u0(.clk(clk,.rst(rst,.clk_1hz(clk_1hz;cnt10 u1(.clk_1hz(clk_1hz,.cnt(

11、cnt,.rst(rst;qiduan u2(.cnt(cnt,.data_out(led;endmodule5. 設(shè)計應(yīng)用工程，LED數(shù)碼管動態(tài)顯示1、2、3、4Verilog HDL設(shè)計；程序設(shè)計：1、計數(shù)器模塊module ledtest(clk,rst,scanclk;input clk,rst;output scanclk;wire scanclk;reg 23:0 cnt;always(posedge clk or negedge rstbeginif(rst=1b0cnt=24d0;elsecnt=cnt+1;endassign scanclk=cnt23;endmodule2、

12、 LED譯碼器模塊module led2(rst,scanclk,led,scan;input rst,scanclk;output 6:0 led;output 3:0 scan;reg 6:0 led;reg 3:0 scan;reg 1:0 state;always(posedge scanclk or negedge rstbeginif(rst=1b0state=2b00;elsestate=state+1;endalways(statebegincase(state2b00:scan=4b0001;2b01:scan=4b0010;2b10:scan=4b0100;2b11:scan=4b1000;endcaseendalways(scanbegincase(scan4b0001:led=7b0000110;4b0010:led=7b1011011;4b0100:led=7b1001111;4b1000:led=7b1100110;default:led=7b0111111;endcaseendendmodule功能仿真圖3、 頂層模塊module ledtop(clk,rst,led,scan;input clk,rst;output 6:0 le