課程設(shè)計(jì)簡單處理器的設(shè)計(jì)與仿真

1、前言11、設(shè)計(jì)任務(wù)22、設(shè)計(jì)說明32.1 處理器原理圖及其組成32.2數(shù)據(jù)傳輸及加減法的實(shí)現(xiàn)32.3處理器所支持的指令及功能說明、指令的編碼規(guī)則42.4指令執(zhí)行的時(shí)序控制43.處理器指令實(shí)現(xiàn)的功能及其具體描述63.1 mv Rx,Ry63.2 mvi Rx,#D73.3 add Rx,Ry和sub Rx,Ry84單元模塊設(shè)計(jì)說明、VHDL代碼及其仿真104.1寄存器RX104.2 寄存器A114.3 加/減法器addsub124.4 寄存器G134.5 指令寄存器IR144.6 計(jì)數(shù)器upcount154.7 復(fù)用器multi164.8 控制單元control184.9 控制指令輸入轉(zhuǎn)換模塊2

2、64.10 16*16點(diǎn)陣顯示控制模塊275 處理器各個(gè)模塊的連接及處理器功能仿真295.1處理器各個(gè)模塊的連接295.2處理器功能仿真29立即數(shù)賦給寄存器R029立即數(shù)賦給寄存器R1295.2.3 寄存器R0的值賦給寄存器R2295.2.4 寄存器R1的值賦給寄存器R329立即數(shù)賦給寄存器R4295.2.6 寄存器R0加上R4賦給R0305.2.7 寄存器R1加上R4賦給R1305.2.6 寄存器R0加上R4賦給R030立即數(shù)賦給寄存器R5305.2.8 寄存器R4減去R5賦給R4305.2.9 寄存器R4減去R0賦給R4306 處理器實(shí)現(xiàn)的功能與操作說明316.1 處理器實(shí)現(xiàn)的功能316.

3、2 處理器相關(guān)的操作說明317 課程設(shè)計(jì)總結(jié)328附錄.34前言VHDL 的英文全名是 Very-High-Speed Integrated Circuit Hardware Description Language，誕生于 1982 年。1987 年底，VHDL被 IEEE 和美國國防部確認(rèn)為標(biāo)準(zhǔn)硬件描述語言。 VHDL主要用于描述數(shù)字系統(tǒng)的結(jié)構(gòu)，行為，功能和接口。除了含有許多具有硬件特征的語句外，VHDL的語言形式和描述風(fēng)格與句法是十分類似于一般的計(jì)算機(jī)高級語言。VHDL的程序結(jié)構(gòu)特點(diǎn)是將一項(xiàng)工程設(shè)計(jì)，或稱設(shè)計(jì)實(shí)體（可以是一個(gè)元件，一個(gè)電路模塊或一個(gè)系統(tǒng)）分成外部（或稱可是部分,及端口)和

4、內(nèi)部（或稱不可視部分），既涉及實(shí)體的內(nèi)部功能和算法完成部分。在對一個(gè)設(shè)計(jì)實(shí)體定義了外部界面后，一旦其內(nèi)部開發(fā)完成后，其他的設(shè)計(jì)就可以直接調(diào)用這個(gè)實(shí)體。這種將設(shè)計(jì)實(shí)體分成內(nèi)外部分的概念是VHDL系統(tǒng)設(shè)計(jì)的基本點(diǎn)。與其他硬件描述語言相比，VHDL具有以下特點(diǎn)：（1）功能強(qiáng)大、設(shè)計(jì)靈活VHDL具有功能強(qiáng)大的語言結(jié)構(gòu)，可以用簡潔明確的源代碼來描述復(fù)雜的邏輯控制。它具有多層次的設(shè)計(jì)描述功能，層層細(xì)化，最后可直接生成電路級描述。VHDL支持同步電路、異步電路和隨機(jī)電路的設(shè)計(jì)，這是其他硬件描述語言所不能比擬的。VHDL還支持各種設(shè)計(jì)方法，既支持自底向上的設(shè)計(jì)，又支持自頂向下的設(shè)計(jì)；既支持模塊化設(shè)計(jì)，又支持層

5、次化設(shè)計(jì)。（2）支持廣泛、易于修改由于VHDL已經(jīng)成為IEEE標(biāo)準(zhǔn)所規(guī)范的硬件描述語言，目前大多數(shù)EDA工具幾乎都支持VHDL，這為VHDL的進(jìn)一步推廣和廣泛應(yīng)用奠定了基礎(chǔ)。在硬件電路設(shè)計(jì)過程中，主要的設(shè)計(jì)文件是用VHDL編寫的源代碼，因?yàn)閂HDL易讀和結(jié)構(gòu)化，所以易于修改設(shè)計(jì)。（3）強(qiáng)大的系統(tǒng)硬件描述能力VHDL具有多層次的設(shè)計(jì)描述功能，既可以描述系統(tǒng)級電路，又可以描述門級電路。而描述既可以采用行為描述、寄存器傳輸描述或結(jié)構(gòu)描述，也可以采用三者混合的混合級描述。另外，VHDL支持慣性延遲和傳輸延遲，還可以準(zhǔn)確地建立硬件電路模型。VHDL支持預(yù)定義的和自定義的數(shù)據(jù)類型，給硬件描述帶來較大的自由

6、度，使設(shè)計(jì)人員能夠方便地創(chuàng)建高層次的系統(tǒng)模型。（4）獨(dú)立于器件的設(shè)計(jì)、與工藝無關(guān)設(shè)計(jì)人員用VHDL進(jìn)行設(shè)計(jì)時(shí)，不需要首先考慮選擇完成設(shè)計(jì)的器件，就可以集中精力進(jìn)行設(shè)計(jì)的優(yōu)化。當(dāng)設(shè)計(jì)描述完成后，可以用多種不同的器件結(jié)構(gòu)來實(shí)現(xiàn)其功能。（5）很強(qiáng)的移植能力VHDL是一種標(biāo)準(zhǔn)化的硬件描述語言，同一個(gè)設(shè)計(jì)描述可以被不同的工具所支持，使得設(shè)計(jì)描述的移植成為可能。（6）易于共享和復(fù)用VHDL采用基于庫（Library）的設(shè)計(jì)方法，可以建立各種可再次利用的模塊。這些模塊可以預(yù)先設(shè)計(jì)或使用以前設(shè)計(jì)中的存檔模塊，將這些模塊存放到庫中，就可以在以后的設(shè)計(jì)中進(jìn)行復(fù)用，可以使設(shè)計(jì)成果在設(shè)計(jì)人員之間進(jìn)行交流和共享，減少硬

7、件電路設(shè)計(jì)。1、設(shè)計(jì)任務(wù)用VHDL設(shè)計(jì)一個(gè)簡單的處理器，并完成相關(guān)的仿真測試。2、設(shè)計(jì)說明2.1 處理器原理圖及其組成圖1是一個(gè)處理器的原理圖，它包含了一定數(shù)量的寄存器、一個(gè)復(fù)用器、一個(gè)加法/減法器（Addsub）,一個(gè)計(jì)數(shù)器和一個(gè)控制單元。圖1 簡單處理器的電路圖2.2數(shù)據(jù)傳輸及加減法的實(shí)現(xiàn)數(shù)據(jù)傳輸實(shí)現(xiàn)過程：16位數(shù)據(jù)從DIN輸入到系統(tǒng)中，可以通過復(fù)用器分配給R0R7和A，復(fù)用器也允許數(shù)據(jù)從一個(gè)寄存器傳通過Bus送到另外一個(gè)寄存器。加法和減法的實(shí)現(xiàn)過程：復(fù)用器先將一個(gè)數(shù)據(jù)通過總線放到寄存器A中，然后將另一個(gè)數(shù)據(jù)放到總線上，加法/減法器對這兩個(gè)數(shù)據(jù)進(jìn)行運(yùn)算，運(yùn)算結(jié)果存入寄存器G中，G中的數(shù)據(jù)又

8、可根據(jù)要求通過復(fù)用器轉(zhuǎn)存到其他寄存器中。2.3處理器所支持的指令及功能說明、指令的編碼規(guī)則表1是該處理所支持的指令表1 操作功能說明mv Rx, RyRx Ry將 Ry 寄存器的值復(fù)制到 Rx 寄存器mvi Rx, #DRx Data將 Data 值 存入 Rx寄存器add Rx, RyRx Rx + Ry先將 Rx 和 Ry寄存器的值相加，再把相加的值存入 Rx寄存器sub Rx, RyRx Rx - Ry先將 Rx 和 Ry 寄存器的值相減，再把相減的值存入 Rx 寄存器所有指令都按9位編碼（取自DIN的高9位）存儲在指令寄存器IR中，編碼規(guī)則為IIIXXXYYY，III表示指令，XXX表

9、示Rx寄存器，YYY表示Ry寄存器。立即數(shù)#D是在mvi指令存儲到IR中之后，通過16位DIN輸入的。如表2所示表22.4指令執(zhí)行的時(shí)序控制有一些指令，如加法指令和減法指令，需要在總線上多次傳輸數(shù)據(jù)，因此需要多個(gè)時(shí)鐘周期才能完成。控制單元使用了一個(gè)兩位計(jì)數(shù)器來區(qū)分這些指令執(zhí)行的每一個(gè)階段。當(dāng)Run信號置位時(shí)，處理器開始執(zhí)行DIN輸入的指令。當(dāng)指令執(zhí)行結(jié)束后，Done信號置位，表3列出四個(gè)指令在執(zhí)行過程中每一個(gè)時(shí)間段置位的控制信號。圖2列出了處理器的狀態(tài)轉(zhuǎn)換圖表3： 時(shí)間指令T0T1T2T3(mv):I0(mvi):I1(add):I2(sub):I3IRinIRinIRinIRinRYout,

10、RXin,DoneDINout,RXin,DoneRXout,AinRXout,Ain-RYout,Gin,AddsubRYout,Gin,Addsub-Gout,RXin,DoneGout,RXin,Done“00”IRin“10”Add/sub“01”mv“11”Add/sub“01”Add/sub“01”mvi“10”Add/sub圖2，處理器狀態(tài)轉(zhuǎn)換圖3.處理器指令實(shí)現(xiàn)的功能及其具體描述3.1 mv Rx,Ry實(shí)現(xiàn)的功能：將寄存器Rx的值賦給寄存器Ry（以mv R0, R5為例）（1 ）計(jì)數(shù)器為“00”時(shí),指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。

11、置位的控制信號如圖3加粗黑線所示。圖3（2）計(jì)數(shù)器為“01”時(shí),首先控制單元根據(jù)設(shè)計(jì)器為“00”時(shí)輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R5的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個(gè)寄存器對寄存器的賦值過程。置位的控制信號和數(shù)據(jù)流如圖4加粗黑線所示。圖43.2 mvi Rx,#D實(shí)現(xiàn)的功能：將的立即數(shù)#D賦給寄存器Rx（以mv R0, #D為例）（1）計(jì)數(shù)器為“00”時(shí),指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖5加粗黑線所示。圖5（2）計(jì)數(shù)器為“01”時(shí),首先控制單元根據(jù)設(shè)計(jì)器為“00”

12、時(shí)輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓DIN的值輸出到總線上，然后控制單元控制寄存器R0將總線上的值鎖存，完成整個(gè)立即數(shù)對寄存器的賦值過程。置位的控制信號和數(shù)據(jù)流如圖6加粗黑線所示。圖63.3 add Rx,Ry和sub Rx,Ry實(shí)現(xiàn)的功能：將寄存器Ry的值加上/減去寄存器Rx的值并賦給寄存器Rx（以add/sub R0,R1為例）。（1）計(jì)數(shù)器為“00”時(shí),指令寄存器的置位控制信號輸入端IRin=1有效，將DIN輸入的數(shù)據(jù)的高9位鎖存。置位的控制信號如圖7加粗黑線所示。圖7（2）計(jì)數(shù)器為“01”時(shí),首先控制單元根據(jù)設(shè)計(jì)器為“00”時(shí)輸入的指令，向復(fù)用器發(fā)出選通控制信

13、號，復(fù)用器根據(jù)該控制信號讓R0的值輸出到總線上，然后控制單元控制寄存器A將總線上的值鎖存。置位的控制信號和數(shù)據(jù)流如圖8加粗黑線所示。圖8（3）計(jì)數(shù)器為“10”時(shí),首先控制單元根據(jù)設(shè)計(jì)器為“00”時(shí)輸入的指令，向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓R1的值輸出到總線上，然后控制單元控制加法/減法器addsub將寄存器A的值和總線上的值相加/相減并輸出，接著寄存器G將加法/減法器addsub的計(jì)算結(jié)果鎖存。置位的控制信號和數(shù)據(jù)流如圖9加粗黑線所示。圖9（4）計(jì)數(shù)器為“11”時(shí),首先控制單元向復(fù)用器發(fā)出選通控制信號，復(fù)用器根據(jù)該控制信號讓寄存器G的值輸出到總線上，寄存器R0將總線上的值進(jìn)行

14、鎖存，完成整個(gè)寄存器與對寄存器見加減法的運(yùn)算過程。置位的控制信號和數(shù)據(jù)流如圖10加粗黑線所示。圖104單元模塊設(shè)計(jì)說明、VHDL代碼及其仿真4.1寄存器RX寄存器R0R7用于數(shù)據(jù)的存儲。當(dāng)時(shí)鐘輸入clock的上升沿到來且RXin=1時(shí)，將數(shù)據(jù)輸入端datain15.0的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout15.0輸出；當(dāng)RXin=0時(shí)，輸出端保持原來的值不變。圖11寄存器RX的VHDL代碼： library ieee;use ieee.std_logic_1164.all;entity RX isport(RXin,clock : in std_logic;datain :in st

15、d_logic_vector(15 downto 0);dataout:out std_logic_vector(15 downto 0) );end RX;architecture behave of RX is signal databuffer:std_logic_vector(15 downto 0);beginprocess(clock,RXin,datain,databuffer)beginif (clock'event and clock='1') then if (RXin='1') then databuffer<=datain;

16、 else databuffer<=databuffer;end if;else databuffer<=databuffer;end if;dataout<=databuffer;end process;end behave;4.2 寄存器A寄存器A用于數(shù)據(jù)的存儲，當(dāng)時(shí)鐘輸入clock的上升沿到來且Ain=1時(shí)，將數(shù)據(jù)輸入端datain15.0的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout15.0輸出；當(dāng)RXin=0時(shí)，輸出端保持原來的值不變。當(dāng)處理加減法時(shí)，將時(shí)間T1時(shí)總線送過來的數(shù)據(jù)暫存，當(dāng)T2時(shí)，將T1時(shí)存儲在A中的數(shù)據(jù)與總線傳輸過來的數(shù)據(jù)在Addsub中進(jìn)行加減運(yùn)

17、算，并將結(jié)果并輸出到寄存器G中。圖12寄存器A的VHDL代碼：library ieee;use ieee.std_logic_1164.all;entity A isport(Ain,clock : in std_logic;datain :in std_logic_vector(15 downto 0);dataout:out std_logic_vector(15 downto 0) );end A;architecture behave of A is signal databuffer:std_logic_vector(15 downto 0);beginprocess(clock,A

18、in,datain,databuffer)beginif (clock'event and clock='1') then if (Ain='1') then databuffer<=datain; else databuffer<=databuffer;end if;else databuffer<=databuffer;end if;dataout<=databuffer;end process;end behave;4.3 加/減法器addsub加/減法器addsub用于處理兩個(gè)輸入的數(shù)據(jù)datain215.0和datain

19、115.0，當(dāng)控制端Addsub=1時(shí)，兩個(gè)數(shù)據(jù)輸入端datain215.0和datain115.0相加并從數(shù)據(jù)輸出端dataout15.0輸出；當(dāng)控制端Addsub=0時(shí)，數(shù)據(jù)輸入端datain215.0減去datain115.0，結(jié)果從數(shù)據(jù)輸出端dataout15.0輸出。圖 13加/減法器addsub的VHDL代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity addsub isport(Addsub : in std

20、_logic;datain1 :in std_logic_vector(15 downto 0);datain2 :in std_logic_vector(15 downto 0);dataout:out std_logic_vector(15 downto 0) );end addsub;architecture behave of addsub is signal databuffer:std_logic_vector(15 downto 0);beginprocess(Addsub,datain1,datain2,databuffer)begin if (Addsub='1

21、9;) then databuffer<=datain2+datain1; elsif (Addsub='0') then databuffer<=datain2-datain1;else databuffer<=databuffer;end if;dataout<=databuffer;end process;end behave;4.4 寄存器G寄存器G用于加減運(yùn)算結(jié)果的存儲，當(dāng)時(shí)鐘輸入clock的上升沿到來且Gin=1時(shí)，將數(shù)據(jù)輸入端datain15.0的數(shù)據(jù)鎖存到寄存器中并從數(shù)據(jù)輸出端dataout15.0輸出；當(dāng)RXin=0時(shí)，輸出端保持原來的

22、值不變。圖14寄存器G的VHDL代碼：library ieee;use ieee.std_logic_1164.all;entity G isport(Gin,clock : in std_logic;datain :in std_logic_vector(15 downto 0);dataout:out std_logic_vector(15 downto 0) );end G;architecture behave of G is signal databuffer:std_logic_vector(15 downto 0);beginprocess(clock,Gin,datain,da

23、tabuffer)beginif (clock'event and clock='1') then if (Gin='1') then databuffer<=datain; else databuffer<=databuffer;end if;else databuffer<=databuffer;end if;dataout<=databuffer;end process;end behave;4.5 指令寄存器IR指令寄存器IR用于對輸入的16為指令進(jìn)行處理，取其高9位。當(dāng)時(shí)鐘輸入clock的上升沿到來且IRin=1時(shí)，取數(shù)

24、據(jù)輸入端datain15.0的高9位將其鎖存到寄存器中并從數(shù)據(jù)輸出端dataout8.0輸出；當(dāng)RXin=0時(shí)，輸出端保持原來的值不變。圖15指令寄存器IR的VHDL代碼library ieee;use ieee.std_logic_1164.all;entity IR isport(IRin,clock : in std_logic;datain :in std_logic_vector(15 downto 0);dataout:out std_logic_vector(8 downto 0) );end IR;architecture behave of IR is signal data

25、buffer:std_logic_vector(8 downto 0);beginprocess(clock,IRin,datain,databuffer)beginif (clock'event and clock='1') then if (IRin='1') then databuffer<=datain(15 downto 7); else databuffer<=databuffer;end if;else databuffer<=databuffer;end if;dataout<=databuffer;end pro

26、cess;end behave;4.6 計(jì)數(shù)器upcount計(jì)數(shù)器upcount用于產(chǎn)生控制單元的輸入脈沖，對控制單元的工作時(shí)序進(jìn)行控制。當(dāng)clear=0時(shí)（清零端clear無效），時(shí)鐘輸入clock每來一個(gè)上升沿，輸出Q1.0加1，所以輸出為00>01>10>11>00不斷循環(huán)；當(dāng)clear=1時(shí)（清零端clear有效），對輸出Q1.0異步清零，與時(shí)鐘無關(guān)。圖16計(jì)數(shù)器upcount的VHDL代碼library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity upcount i

27、sport(clear, clock : in std_logic;Q : out std_logic_vector(1 downto 0);end upcount;architecture Behavior of upcount issignal count : std_logic_vector(1 downto 0);beginprocess (Clock)beginif (clock'event and clock='1') thenif clear='1' then -clear='1' clear is effectivecou

28、nt <= "00"else count<= count+1;end if;end if;end process;Q<=count;end Behavior;4.7 復(fù)用器multi復(fù)用器根據(jù)控制單元的控制信號將指定的輸入數(shù)據(jù)輸出到總線上。來自控制單元的控制信號為R0outR7out、Gout、DINout，輸入數(shù)據(jù)位來自寄存器R0R7、寄存器A、數(shù)據(jù)輸入端DIN，當(dāng)控制信號的某一位為1時(shí)，將其對應(yīng)的輸入數(shù)據(jù)輸出到總線上。圖17復(fù)用器multi的VHDL代碼library ieee;use ieee.std_logic_1164.all;use ieee.

29、std_logic_arith.all;use ieee.std_logic_unsigned.all;entity multi isport(R0in :in std_logic_vector(15 downto 0);R1in :in std_logic_vector(15 downto 0);R2in :in std_logic_vector(15 downto 0);R3in :in std_logic_vector(15 downto 0);R4in :in std_logic_vector(15 downto 0);R5in :in std_logic_vector(15 down

30、to 0);R6in :in std_logic_vector(15 downto 0);R7in :in std_logic_vector(15 downto 0);DIN :in std_logic_vector(15 downto 0);Gin :in std_logic_vector(15 downto 0);R0out :in std_logic;R1out :in std_logic;R2out :in std_logic;R3out :in std_logic;R4out :in std_logic;R5out :in std_logic;R6out :in std_logic;

31、R7out :in std_logic;Gout :in std_logic;DINout :in std_logic;buswire:buffer std_logic_vector(15 downto 0) );end multi;architecture behave of multi is signal select_signal:std_logic_vector(9 downto 0);signal databuffer:std_logic_vector(15 downto 0);beginselect_signal<=R7out&R6out&R5out&

32、R4out&R3out&R2out&R1out&R0out&Gout&DINout;process(databuffer,R0in,R1in,R2in,R3in,R4in,R5in,R6in,R7in,DIN,Gin,R7out,R6out,R5out,R4out,R3out,R2out,R1out,R0out,Gout,DINout)begincase select_signal iswhen"0000000001"=>databuffer<=DIN;when"0000000010"=>

33、databuffer<=Gin;when"0000000100"=>databuffer<=R0in;when"0000001000"=>databuffer<=R1in;when"0000010000"=>databuffer<=R2in;when"0000100000"=>databuffer<=R3in;when"0001000000"=>databuffer<=R4in;when"0010000000"

34、=>databuffer<=R5in;when"0100000000"=>databuffer<=R6in;when"1000000000"=>databuffer<=R7in;when others=>null;end case;buswire<=databuffer;end process;end behave;4.8 控制單元control控制單元根據(jù)計(jì)數(shù)器發(fā)出的脈沖和DIN輸入的操作指令對整個(gè)系統(tǒng)的其他模塊進(jìn)行控制，完成指定的操作。圖18控制單元control的VHDL代碼library ieee;

35、use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity control isport(Run :in std_logic;Reset :in std_logic;DIN_IR_9 :in std_logic_vector(8 downto 0);count :in std_logic_vector(1 downto 0);IRin :out std_logic;Gout :out std_logic;DINout :out std_logic;R0in,R1i

36、n,R2in,R3in,R4in,R5in,R6in,R7in:out std_logic;R0out,R1out,R2out,R3out,R4out,R5out,R6out,R7out :out std_logic;Gin :out std_logic;Ain :out std_logic;Addsub :out std_logic;Done :out std_logic;clear :out std_logic);end control;architecture behave of control is -type state is (state0,state1,state2,state3

37、);-signal current_state,next_state:state;signal IR_buffer:std_logic_vector (8 downto 0);-signal temp0:std_logic_vector (2 downto 0);beginprocess(Run,reset,count)beginIR_buffer<=DIN_IR_9;if (Run='1' and reset='0' )then case count iswhen "00"=> IRin<='0' Gout

38、<='0'DINout<='0'R0in<='0'R1in<='0'R2in<='0'R3in<='0'R4in<='0'R5in<='0'R6in<='0'R7in<='0'R0out<='0'R1out<='0'R2out<='0'R3out<='0'R4out<='0&#

39、39;R5out<='0'R6out<='0'R7out<='0'Gin<='0'Ain<='0'Addsub<='0'Done<='0'clear<='0' IRin<='1' - -state1-when "01"=> -ttttttttttttttttttttttttttttttttttttttttt if(IR_buffer(8 downto 6)="00

40、0") then - mv Rx,Ry state1IRin<='0' Gout<='0'DINout<='0'R0in<='0'R1in<='0'R2in<='0'R3in<='0'R4in<='0'R5in<='0'R6in<='0'R7in<='0'R0out<='0'R1out<='0'R2ou

41、t<='0'R3out<='0'R4out<='0'R5out<='0'R6out<='0'R7out<='0'Gin<='0'Ain<='0'Addsub<='0'Done<='0'clear<='0' case IR_buffer(2 downto 0) is when"000"=> R0out<='1'

42、 - test1_signal<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when &qu

43、ot;101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=> null; end case; when"001"=> R1out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001

44、"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='

45、;1' when others=> null; end case; when"010"=> R2out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1'

46、; when "100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=> null; end case; when"011"=> R3out<='1' case IR_buffer(5 downto 3) is when

47、 "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6i

48、n<='1' when "111"=>R7in<='1' when others=> null; end case; when"100"=> R4out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<=

49、'1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=> null; end case; when"101"=>

50、R5out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101&quo

51、t;=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=> null; end case; when"110"=> R6out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>

52、;R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' wh

53、en others=> null; end case; when"111"=> R7out<='1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when &qu

54、ot;100"=>R4in<='1' when "101"=>R5in<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=> null; end case; when others=>null; end case; Done<='1' clear<='1' -ttttttttttttttt

55、tttttttttttttttttttttttttt elsif(IR_buffer(8 downto 6)="001") then - mvi Rx,#D state1 IRin<='0' Gout<='0'DINout<='0'R0in<='0'R1in<='0'R2in<='0'R3in<='0'R4in<='0'R5in<='0'R6in<='0'R

56、7in<='0'R0out<='0'R1out<='0'R2out<='0'R3out<='0'R4out<='0'R5out<='0'R6out<='0'R7out<='0'Gin<='0'Ain<='0'Addsub<='0'Done<='0'clear<='0' DINout<=

57、'1' case IR_buffer(5 downto 3) is when "000"=>R0in<='1' when "001"=>R1in<='1' when "010"=>R2in<='1' when "011"=>R3in<='1' when "100"=>R4in<='1' when "101"=>R5i

58、n<='1' when "110"=>R6in<='1' when "111"=>R7in<='1' when others=>null; end case; Done<='1' clear<='1' -= -ppppppppppppppppppppppppppppppppppppppp elsif(IR_buffer(8 downto 6)="010") then - add Rx,Ry state1IRi

59、n<='0' Gout<='0'DINout<='0'R0in<='0'R1in<='0'R2in<='0'R3in<='0'R4in<='0'R5in<='0'R6in<='0'R7in<='0'R0out<='0'R1out<='0'R2out<='0'R3out<='0&

60、#39;R4out<='0'R5out<='0'R6out<='0'R7out<='0'Gin<='0'Ain<='0'Addsub<='0'Done<='0'clear<='0' case IR_buffer(5 downto 3) is when "000"=>R0out<='1' when "001"=>R1out<='1' when "010"=>R2out<='1' when "011"=>R3out<='1' when "100"=>R4out<='1' when "101"=>R5out<='1' when "110&