數(shù)字秒表的設(shè)計(jì)的vhdl語(yǔ)言

1、數(shù)字秒表的VHDL語(yǔ)言的程序設(shè)計(jì)本秒表計(jì)時(shí)器用于體育競(jìng)賽及各種要求有較精確時(shí)的各領(lǐng)域。此計(jì)時(shí)器是用一塊專用的芯片，用VHDL語(yǔ)言描述的。它除開(kāi)關(guān)、時(shí)鐘和顯示功能以外，它還包括1/100s計(jì)時(shí)器所有的控制和定時(shí)功能，其體積小，攜帶方便。計(jì)時(shí)器的設(shè)計(jì)功能：（1） 精度應(yīng)大于1/100s（2） 計(jì)時(shí)器的最長(zhǎng)計(jì)時(shí)時(shí)間為1小時(shí)在一般的短時(shí)間計(jì)時(shí)應(yīng)用中，1小時(shí)應(yīng)該足夠了。為此需要一個(gè)6位顯示器，顯示最長(zhǎng)時(shí)間為59分59.99秒。（3） 設(shè)置復(fù)位和啟/停開(kāi)關(guān)復(fù)位開(kāi)關(guān)用來(lái)使計(jì)時(shí)器清0，并作好清0準(zhǔn)備。啟/停開(kāi)關(guān)的使用方法與傳統(tǒng)的機(jī)械計(jì)時(shí)器相同，即按一下啟/停開(kāi)關(guān)，啟動(dòng)計(jì)時(shí)器開(kāi)始計(jì)時(shí)，再按一下啟/停開(kāi)關(guān)計(jì)時(shí)終止

2、。復(fù)位開(kāi)關(guān)可以在任何情況下使用，即使在計(jì)時(shí)過(guò)程中，只要按一下復(fù)位開(kāi)關(guān)，計(jì)時(shí)進(jìn)程應(yīng)立即終止，并對(duì)計(jì)時(shí)器清零。設(shè)計(jì)方案：為了便于描述，將整個(gè)計(jì)時(shí)控制芯片分成5個(gè)子模塊：鍵輸入子模塊（keyin）,時(shí)鐘產(chǎn)生子模塊（clkgen）,控制子模塊（ctrl）,定時(shí)計(jì)數(shù)子模塊（cntclk）和顯示子模塊（disp）。芯片設(shè)計(jì)：各模塊程序及生成的符號(hào)文件如下：keyin模塊設(shè)計(jì)該模塊的描述是為了產(chǎn)生單個(gè)復(fù)位脈沖res和啟停脈沖stst.整個(gè)功能模塊用兩個(gè)進(jìn)程語(yǔ)句描述。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all

3、;entity keyin isport(reset,start_stop,clk :in std_logic;res,stst :out std_logic);end entity;architecture a of keyin issignal res0,res1,stst0,stst1 :std_logic;beginprocess(clk)beginif(clkevent and clk=0)thenres1=res0;res0=reset;stst1=stst0;stst0=start_stop;end if;end process;process(res0,res1,stst0,s

4、tst1)beginres=clk and res0 and (not res1);stst=clk and stst0 and (not stst1);end process;end a;clkgen模塊設(shè)計(jì)該模塊的功能是產(chǎn)生100Hz的計(jì)時(shí)允許信號(hào)cntclk和25Hz的寬度為1ms的鍵輸入時(shí)鐘信號(hào)keycek.LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt10 IS PORT (reset,en,clk:IN STD_LOGIC; carry:OUT STD_LOGIC

5、; q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT10;ARCHITECTURE rtl OF cnt10 IS SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca :STD_LOGIC;BEGIN PROCESS(clk) BEGIN IF(clkEVENT AND clk=1)THEN IF(reset=1)THEN qs=0000; ELSIF(en=1) THEN IF(qs=1001) THEN qs= 0000; ca=0; ELSIF(qs=1000) THEN qs= qs+1; ca=1

6、; ELSELIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt4 IS PORT (reset,en,clk:IN STD_LOGIC; carry :OUT STD_LOGIC; q :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);END CNT4;ARCHITECTURE rtl OF cnt4 IS SIGNAL qs :STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL ca :STD_LOGIC;BEGIN PROCESS(cl

7、k) BEGIN IF(clkEVENT AND clk=1)THEN IF(reset=1)THEN qs=00; ELSIF (EN=1)THEN IF(qs=11) THEN qs= 00; ca=0; ELSIF(qs=10) THEN qs= qs+1; ca=1; ELSE qs=qs+1; ca=0; END IF; END IF; END IF; END PROCESS; PROCESS(ca) BEGIN q=qs; carry=ca AND en; END PROCESS; END rtl;ctrl子模塊該模塊的功能是產(chǎn)生計(jì)時(shí)計(jì)數(shù)模塊的計(jì)數(shù)允許信號(hào)cntenlibrary

8、ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity ctrl isport(sysres,res,stst,cntclk:in std_ulogic;centen:out std_ulogic);end ctrl;architecture rtl of ctrl issignal enb1:std_ulogic;begin process(stst,sysres,res)begin if(sysres=1 or res=1) thenenb1=0;elsif(ststevent and stst=1) the

9、nenb1=not enb1;end if;end process;centen=enb1 and cntclk;end rtl;cntblk模塊設(shè)計(jì)該模塊的功能是實(shí)現(xiàn)計(jì)時(shí)計(jì)數(shù)，它由四個(gè)十進(jìn)制計(jì)數(shù)器和兩個(gè)六進(jìn)制計(jì)數(shù)器串結(jié)而成。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt10 IS PORT (reset,en,clk:IN STD_LOGIC; carry:OUT STD_LOGIC; q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT1

10、0;ARCHITECTURE rtl OF cnt10 IS SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca :STD_LOGIC;BEGIN PROCESS(clk) BEGIN IF(clkEVENT AND clk=1)THEN IF(reset=1)THEN qs=0000; ELSIF(en=1) THEN IF(qs=1001) THEN qs= 0000; ca=0; ELSIF(qs=1000) THEN qs= qs+1; ca=1; ELSE qs=qs+1; ca=0; END IF; END IF; END IF;

11、END PROCESS; PROCESS(ca,en) BEGIN q=qs; carry=ca AND en; END PROCESS; END rtl; LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt6 IS PORT (reset,en,clk:IN STD_LOGIC; carry :OUT STD_LOGIC; q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT6;ARCHITECTURE rtl OF cnt6 IS SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca :STD_LOGIC;BEGIN PROCESS(clk) BEGIN IF(clkEVENT AND clk=1)THEN IF(reset=1)THEN qs=0000; ELSIF(en=1)THEN IF(qs=010