EDA實(shí)驗(yàn)五狀態(tài)機(jī)

1、實(shí)驗(yàn)五有限狀態(tài)機(jī)0900210204吳韋艷一、實(shí)驗(yàn)?zāi)康模罕敬螌?shí)驗(yàn)通過Verilog硬件語言編寫摩爾型有限狀態(tài)機(jī)和米勒型有限狀態(tài)機(jī)，掌握采用有限狀態(tài)機(jī)產(chǎn)生各種控制信號(hào)的原理，熟悉如何選用適宜的有限狀態(tài)機(jī)進(jìn)行電路設(shè)計(jì)，通過實(shí)驗(yàn)進(jìn)一步了解原理圖編輯方法和仿真方法。二、實(shí)驗(yàn)要求：1、利用Verilog硬件語言，參考提供的源程序，設(shè)計(jì)一個(gè)采用摩爾型有限狀態(tài)機(jī)實(shí)現(xiàn)的流水燈控制程序；2、利用Verilog硬件語言，參考提供的源程序，設(shè)計(jì)一個(gè)采用米勒型有限狀態(tài)機(jī)實(shí)現(xiàn)的串行口發(fā)送程序；3、利用Verilog硬件語言，參考提供的源程序，設(shè)計(jì)一個(gè)采用米勒型有限狀態(tài)機(jī)實(shí)現(xiàn)的串行口接收程序；4、利用原理圖編輯方法，將串

2、行口發(fā)送和接收模塊進(jìn)行連接，實(shí)現(xiàn)完整的串行通信電路，并對該電路進(jìn)行仿真。三、實(shí)驗(yàn)內(nèi)容1、米勒型有限狀態(tài)機(jī)實(shí)現(xiàn)的串行口發(fā)送源程序modules_tx(clk,en,dain,txd);inputclk,en;input7:0dain;outputtxd;reg7:0da_temp;regtxd;reg3:0state;parameterswait=4'b0000,star=4'b0001,s1=4'b0010,s2=4'b0011,s3=4'b0100,s4=4'b0101,s5=4'b0110,s6=4'b0111,s7=4

3、9;b1000,s8=4'b1001,stop=4'b1010;always(posedgeen)da_temp<=dain;always(posedgeclk)if(!en)beginstate<=swait;txd<=1;endelsecase(state)swait:beginstate<=star;txd<=1;endstar:beginstate<=s1;txd<=0;end/狀態(tài)轉(zhuǎn)換s1:beginstate<=s2;txd<=da_temp7;ends2:beginstate<=s3;txd<=da

4、_temp6;ends3:beginstate<=s4;txd<=da_temp5;ends4:beginstate<=s5;txd<=da_temp4;ends5:beginstate<=s6;txd<=da_temp3;ends6:beginstate<=s7;txd<=da_temp2;ends7:beginstate<=s8;txd<=da_temp1;ends8:beginstate<=stop;txd<=da_temp0;endstop:beginstate<=stop;txd<=1;endendc

5、aseendmodule2、米勒型有限狀態(tài)機(jī)實(shí)現(xiàn)的串行口接收源程序modules_rx(clk,dain,daout);inputclk,dain;output7:0daout;reg7:0daout;reg7:0da_temp;reg3:0state;parameterstar=4'b0000,s1=4'b0010,s2=4'b0011,s3=4'b0100,s4=4'b0101,s5=4'b0110,s6=4'b0111,s7=4'b1000,s8=4'b1001,stop=4'b1010;always(neg

6、edgeclk)case(state)star:if(dain)state<=star;elsestate<=s1;/數(shù)據(jù)開始位為s1:beginstate<=s2;da_temp7<=dain;end/s2:beginstate<=s3;da_temp6<=dain;ends3:beginstate<=s4;da_temp5<=dain;ends4:beginstate<=s5;da_temp4<=dain;ends5:beginstate<=s6;da_temp3<=dain;ends6:beginstate<=

7、s7;da_temp2<=dain;ends7:beginstate<=s8;da_temp1<=dain;end/8s8:beginstate<=stop;da_temp0<=dain;end/狀態(tài)轉(zhuǎn)換個(gè)狀態(tài)數(shù)據(jù)結(jié)束位為1stop:if(!dain)state<=stop;elsebeginstate<=star;daout<=da_temp;endendcaseEndmodule3、由stx和srx組成的電路iPariiTi*Wvau«cwaitstarECCC1FalBFCWELL3BC'tC'34S5ETC?&#

8、163;anonrB-1CCCDMC-CrF?ETPeraniDterValue3tdrJB'MOOr,rooirq汗碩rb3FOiaTs4ccior史e-0110-fe'0111'打EmocraSemoofstepE'-iaicr蘇:布F'faJi1-1.-11-1'«fc'4、對以上電路做波形仿真Im逆叫mmi"hi.w邛牛叫皿瓢牛旺"it"列f叫）姑0叫u；1dk,iuomwuanrjMnrainoninonn:_'_'u司Uisi嘛.iwm；.；.«ewm.tilo

9、jo.L.oamca.伽典此.挪觀鬼.忡照片賦.咔.£:;i帥:.o(DMa.uuuLiirulttirjirrr_u-lo-_rQliMiimnoffKKiiinclYFinm|'ii|iwtjirm前酷成pwMpM期*略傾P祚O.DhsL甄小砒她麟也.§夠M(0虹直i.如9M.p«-papH1mwimmnmmnnwmjnimmimniwniwjoiuinnnnnimmnmrjmuinwjMnvuirjifjuujLTimjir4_IL11_1LJ*muji頊1曰1叫IfJ3PIUNIjnwxv.I0LLUDAiKwm網(wǎng)L3）；口岫X：舞m網(wǎng)N_Iin1""1.|_1r#r-*1BLLJH/rL_1_Ln_""Lr,1ll-.in1L_r一rOilJT-Tj_L_-_r-_-_gBJ頑.!1.皿國回，：Lial