時(shí)序邏輯電路和組合邏輯電路的設(shè)計(jì)

1、時(shí)序邏輯電路設(shè)計(jì)時(shí)序邏輯電路設(shè)計(jì)時(shí)鐘信號(hào)時(shí)鐘信號(hào)在時(shí)序電路中，是以時(shí)鐘信號(hào)作為驅(qū)動(dòng)信號(hào)的，也就是說時(shí)在時(shí)序電路中，是以時(shí)鐘信號(hào)作為驅(qū)動(dòng)信號(hào)的，也就是說時(shí)序電路是在時(shí)鐘信號(hào)的邊沿到來時(shí)，它的狀態(tài)才會(huì)發(fā)生序電路是在時(shí)鐘信號(hào)的邊沿到來時(shí)，它的狀態(tài)才會(huì)發(fā)生改變。改變。在用在用VHDL描述時(shí)序邏輯電路時(shí)，通常采用時(shí)鐘進(jìn)程的形式描述時(shí)序邏輯電路時(shí)，通常采用時(shí)鐘進(jìn)程的形式來描述，也就是說，時(shí)序邏輯電路中進(jìn)程的敏感信號(hào)是來描述，也就是說，時(shí)序邏輯電路中進(jìn)程的敏感信號(hào)是時(shí)鐘信號(hào)。時(shí)鐘信號(hào)。時(shí)鐘作為敏感信號(hào)的描述方式有兩種：時(shí)鐘作為敏感信號(hào)的描述方式有兩種：(1) 時(shí)鐘信號(hào)顯示地出現(xiàn)在時(shí)鐘信號(hào)顯示地出現(xiàn)在PROC

2、ESS語句后面的敏感信號(hào)語句后面的敏感信號(hào)表中。表中。 (2) 時(shí)鐘信號(hào)沒有顯示地出現(xiàn)在時(shí)鐘信號(hào)沒有顯示地出現(xiàn)在PROCESS語句后面的敏語句后面的敏感信號(hào)表中，而是出現(xiàn)在感信號(hào)表中，而是出現(xiàn)在WAIT語句的后面。語句的后面。 在時(shí)序邏輯電路中，時(shí)鐘是采用邊沿來觸發(fā)的，時(shí)鐘在時(shí)序邏輯電路中，時(shí)鐘是采用邊沿來觸發(fā)的，時(shí)鐘邊沿分為上升沿和下降沿：邊沿分為上升沿和下降沿：（2） 下降沿描述下降沿描述描述描述1：label1：PROCESS（clk）BEGINIF（clkEVENT AND clk = 0）THENAND PROCESS；描述描述2：label2：PROCESS（clk）BEGINWA

3、IT UNTIL clk = 0；AND PROCESS； （1） 上升沿描述上升沿描述:描述描述1：label1：PROCESS（clk）BEGINIF（clkEVENT AND clk = 1）THENAND PROCESS；描述描述2：label2：PROCESS（clk）BEGINWAIT UNTIL clk = 1；AND PROCESS；JK觸發(fā)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JKff_v1 IS PORT(J,K: IN STD_LOGIC; clk: IN STD_LOGIC; set: IN STD_LOGIC

4、; reset: IN STD_LOGIC; Q,QB: OUT STD_LOGIC);END JKff_v1;ARCHITECTURE behave OF JKff_v1 IS SIGNAL Q_temp,QB_temp: STD_LOGIC;BEGIN PROCESS (clk,set,reset) BEGIN IF (set =0 AND reset =1)THEN Q_temp = 1; QB_temp = 0; ELSIF (set =1 AND reset =0)THEN Q_temp = 0; QB_temp = 1; ELSIF (clkEVENT AND clk = 1)TH

5、EN IF(J=0 AND K=1)THEN Q_temp = 0; QB_temp = 1 ELSIF(J=1 AND K=0)THEN Q_temp = 1; QB_temp = 0; ELSIF(J=1 AND K=1)THEN Q_temp = NOT Q_temp ; QB_temp = NOT QB_temp; END IF; END IF; Q = Q_temp; QB = QB_temp;END PROCESS;END behave；JK觸發(fā)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned

6、.all;entity JK2 isport(clk: in std_logic;j,k: in std_logic; q,qn: out std_logic);end JK2;architecture struc of JK2 is signal q_temp:std_logic:=0; signal jk:std_logic_vector(1 downto 0);begin jkq_tempq_tempq_tempq_tempq_temp=X; end case; end if; q=q_temp; qn=not q_temp;end process;end struc;T觸發(fā)器Proce

7、ss(clk)begin if(clkevent and clk=1) then if(t = 1) then q = not(q); else q = q; end if; end if;end process;D鎖存器設(shè)計(jì)鎖存器設(shè)計(jì) CLR是復(fù)位控制輸入端，當(dāng)是復(fù)位控制輸入端，當(dāng)CLR=0時(shí)，時(shí)，8位數(shù)據(jù)輸出位數(shù)據(jù)輸出Q7.0=00000000。ENA是使能控制輸入端，當(dāng)是使能控制輸入端，當(dāng)ENA=1時(shí)，鎖存器處于工作狀態(tài)，輸出時(shí)，鎖存器處于工作狀態(tài)，輸出Q7.0D7.0；ENA=0時(shí)，鎖存器的狀態(tài)保持不變。時(shí)，鎖存器的狀態(tài)保持不變。OE是是三態(tài)輸出控制端，當(dāng)三態(tài)輸出控制端，當(dāng)OE=1時(shí)，

8、輸出為高阻態(tài)；時(shí)，輸出為高阻態(tài)；OE=0時(shí)，鎖存器為正常輸出狀態(tài)。時(shí)，鎖存器為正常輸出狀態(tài)。 具有三態(tài)輸出的具有三態(tài)輸出的8D鎖存器元件符號(hào)鎖存器元件符號(hào)用用VHDL描述的描述的8D鎖存器源程序如下：鎖存器源程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch8 ISPORT(clr,clk,ena,oe:IN STD_LOGIC; d:IN STD_LOGIC_VECTOR(7 DOWNTO 0); q:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END latch8;ARCHITECTURE on

9、e OF latch8 ISSIGNAL q_temp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN u1:PROCESS(clk,clr,ena,oe) BEGINIF clr=0 THEN q_temp = 00000000; ELSIF clkEVENT AND clk=1 THENIF (ena=1) THEN q_temp = d;END IF; END IF; IF oe=1 THEN q = ZZZZZZZZ; ELSE q = q_temp; END IF; END PROCESS u1;END one; 8位雙向移位寄存器元件符號(hào)位雙向移位寄存器元件

10、符號(hào) CLR是復(fù)位控制輸入端；是復(fù)位控制輸入端；LOD是預(yù)置控制輸入端；是預(yù)置控制輸入端；S是移位方向控制輸入端，當(dāng)是移位方向控制輸入端，當(dāng)S=1時(shí)，是右移移位寄存器，時(shí)，是右移移位寄存器，S=0時(shí)，是左移移位寄存器；時(shí)，是左移移位寄存器；DIR是右移串入輸入信號(hào)；是右移串入輸入信號(hào)；DIL是左移串入輸入信號(hào)。是左移串入輸入信號(hào)。 8位雙向移位寄存器設(shè)計(jì)位雙向移位寄存器設(shè)計(jì)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY rlshift ISPORT(clr,lod,clk,s,dir,dil:IN BIT; d:IN BIT_VECTOR(7

11、DOWNTO 0); q:BUFFER BIT_VECTOR(7 DOWNTO 0);END rlshift;ARCHITECTURE one OF rlshift IS SIGNAL q_temp:BIT_VECTOR(7 DOWNTO 0); BEGIN PROCESS(clr,clk,lod,s,dir,dil) BEGIN IF clr=0 THEN q_temp = 00000000; ELSIF clkEVENT AND clk=1 THENIF (lod=1) THENq_temp = d; ELSIF (S=1) THEN FOR i IN 7 downto 1 LOOP -實(shí)

12、現(xiàn)右移操作實(shí)現(xiàn)右移操作 q_temp(i-1) = q(i); END LOOP ;q_temp(7) = dir;ELSE FOR i IN 0 TO 6 LOOP -實(shí)現(xiàn)左移操作實(shí)現(xiàn)左移操作 q_temp(i+1) = q(i); END LOOP ;q_temp(0) = dil;END IF; END IF;q = q_temp; END PROCESS;END one;8位二進(jìn)制加減計(jì)數(shù)器元件符號(hào)位二進(jìn)制加減計(jì)數(shù)器元件符號(hào)CLR是復(fù)位控制輸入端；是復(fù)位控制輸入端；ENA是使能控制輸入端；是使能控制輸入端；LOAD是預(yù)置控制輸入端；是預(yù)置控制輸入端；D7.0是是8位并行數(shù)據(jù)輸入位并行數(shù)

13、據(jù)輸入端；端；UPDOWN是加減控制輸入端，當(dāng)是加減控制輸入端，當(dāng)UPDOWN=0時(shí)，時(shí)，計(jì)數(shù)器作加法操作，計(jì)數(shù)器作加法操作，UPDOWN=1時(shí)，計(jì)數(shù)器作減法操時(shí)，計(jì)數(shù)器作減法操作；作；COUT是進(jìn)是進(jìn)/借位輸出端。借位輸出端。 8位二進(jìn)制加減計(jì)數(shù)器設(shè)計(jì)位二進(jìn)制加減計(jì)數(shù)器設(shè)計(jì)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY updowncnt8 IS PORT(clr,clk,ena,load,updown:IN STD_LOGIC; d:IN INTEGER RANGE 0 TO 255; cout:OUT STD_LOGIC; q:BUFFER

14、 INTEGER RANGE 0 TO 255);END updowncnt8;ARCHITECTURE one OF updowncnt8 ISBEGIN PROCESS(clk,ena,clr,d,load,updown) BEGIN IF CLR=0 THENq = 0; ELSIF clkEVENT AND clk=1 THENIF load = 1 THEN q = d; ELSIF ena=1 THEN IF updown = 0 THEN q = q+1; IF q = 255 THEN COUT = 1; END IF; ELSE q = q-1; IF q = 0 THEN

15、COUT = 0; END IF; END IF; END IF; END IF; END PROCESS;END one; 60進(jìn)制遞增計(jì)數(shù)器進(jìn)制遞增計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee std_ logic_ unsigned. all;ENTITY cntm60v IS PORT( en : IN std_logic; clear : IN std_logic; load : IN std_logic; dl,dh : IN std_logic_vector(3 down to 0); clk : IN std_logi

16、c; cout : out std_logic; ql : buffer std_logic_vector(3 downto 0); qh : buffer std_logic_vector(3 downto 0) );END cntm60v;ARCHITECTURE behave OF cntm60v IS signal ent2 : std_logic;BEGIN PROCESS (clk) VARIABLE tmpl,tmph :std_logic_vector(3 downto 0); BEGIN IF(clear=0) THEN tmpl:=0000; tmph:=“0000”; E

17、LSIF (clkEVENT AND clk = 1) THEN 異步清零異步清零IF load=0 THEN tmpl:=dl; tmph:=dh; elseif (en=1) then if (tmpl=1001) then tmpl:=“0000”; if(tmph=0101) then tmph:=“0000”; else tmph:=tmph+1; end if; else tmpl:=tmpl+1; end if; 同步置數(shù)同步置數(shù)個(gè)位計(jì)數(shù)器個(gè)位計(jì)數(shù)器9+1=0十位計(jì)數(shù)器十位計(jì)數(shù)器5+1=0 59+1=0end IF; END IF; ql = tmpl; ent2 = tmpl(

18、3) and tmpl(0) and en; qh=tmph; cout decode decode decode decode decode = X “00”; end case; end process; IIIIIIII01324567AAA0128線-3線編碼器編碼器編碼器 用一組二進(jìn)制代碼按一定規(guī)則表示給定字母、數(shù)字、符號(hào)等信息用一組二進(jìn)制代碼按一定規(guī)則表示給定字母、數(shù)字、符號(hào)等信息的方法稱為編碼，能夠?qū)崿F(xiàn)這種編碼功能的邏輯電路稱為編碼器。的方法稱為編碼，能夠?qū)崿F(xiàn)這種編碼功能的邏輯電路稱為編碼器。 輸入輸入 輸出輸出I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 1

19、 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1 8線線3線編碼器真值表線編碼器真值表 8線線3線編碼器邏輯表達(dá)式：線編碼器邏輯表達(dá)式：采用行為描述方式的采用行為描述方式的8線線3線編碼器線編碼器VHDL源代碼源代碼 （依據(jù)邏依據(jù)邏輯表達(dá)式）輯表達(dá)式）LIBRARY IEEE;USE IEEE.STD_LOGI

20、C_1164.ALL;ENTITY coder83_v1 IS PORT(I0,I1,I2,I3,I4,I5,I6,I7: IN STD_LOGIC; A0,A1,A2: OUT STD_LOGIC);END coder83_v1;ARCHITECTURE behave OF coder83_v1 ISBEGIN A2 = I4 OR I5 OR I6 OR I7; A1 = I2 OR I3 OR I6 OR I7; A0 A A A A A A A A =000; END CASE; END PROCESS;END dataflow; 優(yōu)先編碼器優(yōu)先編碼器1優(yōu)先編碼器II7I6II0III

21、8線-3線432574148GSEOAA21A0EI46756723670123456712345674567567012345671)(IIIIIIIIIIEIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIEIEIA0123456701234567IIIIIIIIEIIIIIIIIIEIEIGS135745723576701234567234567456767012345670)(IIIIIIIIIIIIIEIIIIIIIIIIIIIIIIIIIIIIIIIIIIIEIEIA01234567IIIIIIIIEIEO45670123456712345672345673456701

22、2345672)(IIIIEIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIEIEIA 輸輸 入入 輸出輸出EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 0 1 0 10 0 1 1 1 1 1 1 1 1 0 0 10 0 1 1 1 1 1 1

23、1 1 1 1 0 1 74148優(yōu)先編碼器真值表優(yōu)先編碼器真值表 （反碼編碼方案）（反碼編碼方案）以以74148邏輯表達(dá)式為依據(jù)，按行為描述方式編邏輯表達(dá)式為依據(jù)，按行為描述方式編寫的寫的VHDL源代碼如源代碼如 下：下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY prioritycoder83_v1 IS PORT(I7,I6,I5,I4,I3,I2,I1,I0 : IN STD_LOGIC; EI:IN STD_LOGIC; A2,A1,A0: OUT STD_LOGIC; GS,EO:OUT STD_LOGIC);END priori

24、tycoder83_v1;ARCHITECTURE behave OF prioritycoder83_v1BEGIN A2 = EI OR (I7 AND I6 AND I5 AND I4); A1 = EI OR (I7 AND I6 AND I3 AND I2) OR (I7 AND I6 AND NOT I5) OR (I7 AND I6 AND NOT I4) ; A0 = EI OR (I7 AND NOT I6) OR (I7 AND I5 AND NOT I4) OR (I7 AND I5 AND I3 AND I1) OR (I7 AND I5 AND I3 AND NOT

25、I2); GS = EI OR (I7 AND I6 AND I5 AND I4 AND I3 AND I2 AND I1 AND I0); EO Y Y Y Y Y Y Y Y =01111111; END CASE; ELSE Y =11111111; END IF; END PROCESS;END dataflow;74151 8選選1數(shù)據(jù)選擇器真值表數(shù)據(jù)選擇器真值表 輸入輸出使能地址選擇YYbGA2A1A01XXX010000D0D00001D1D10010D2D20011D3D30100D4D40101D5D50110D6D60111D7D7DG0DD1Y8選1數(shù)據(jù)選擇器D74151

26、3DDY5D4276D10AA2A多路選擇器多路選擇器 參考參考74151的真值表，采用的真值表，采用IF語句結(jié)構(gòu)編寫的語句結(jié)構(gòu)編寫的VHDL源代碼如下：源代碼如下： LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux8_v2 IS PORT(A: IN STD_LOGIC_VECTOR (2 DOWNTO 0); D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; G:IN STD_LOGIC; Y: OUT STD_LOGIC; YB:OUT STD_LOGIC);END mux8_v2;ARCHITECTURE

27、dataflow OF mux8_v2 IS BEGIN PROCESS (A,D0,D1,D2,D3,D4,D5,D6,D7,G) BEGIN IF (G =1) THEN Y =0; YB =1; ELSIF(G=0AND A=000)THEN Y = D0; YB = NOT D0; ELSIF(G=0AND A=001)THEN Y = D1; YB = NOT D1; ELSIF(G=0AND A=010)THEN Y = D2; YB = NOT D2; ELSIF(G=0AND A=011)THEN Y = D3; YB = NOT D3; ELSIF(G=0AND A=100)

28、THEN Y = D4; YB = NOT D4; ELSIF(G=0AND A=101)THEN Y = D5; YB = NOT D5; ELSIF(G=0AND A=110)THEN Y = D6; YB = NOT D6; ELSE Y = D7; YB = NOT D7; END IF; END PROCESS; END dataflow; 參考參考74151的真值表，采用的真值表，采用CASE語句結(jié)構(gòu)編寫的語句結(jié)構(gòu)編寫的VHDL源代碼如下源代碼如下 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux8_v3 IS PORT(A2,

29、A1,A0: IN STD_LOGIC; D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; G:IN STD_LOGIC; Y: OUT STD_LOGIC; YB:OUT STD_LOGIC);END mux8_v3;ARCHITECTURE dataflow OF mux8_v3 IS SIGNAL comb: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN comb Y = D0; YB Y = D1; YB Y = D2; YB Y = D3; YB Y = D4; YB Y = D5; YB Y = D6; YB Y = D7; YB Y =0; YB B、A B) THEN YA =1; Y