EDA程序設(shè)計(jì)試題及答案

1、1 請(qǐng)畫出下段程序的真值表，并說(shuō)明該電路的功能。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa IS PORT( oe,dir :IN STD_LOGIC ; a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 ) ; END aaa ;ARCHITECTURE ar OF aaa ISBEGIN PROCESS(oe , dir ) 輸入 輸出 BEGIN a1 a0 x3 x2 x1 x0 IF oe=0 THEN a<=”zzzzzzzz”; b<=”zzzzzzzz”; 0 0 0 0 0

2、1 ELSIF oe=1 THEN 0 1 0 0 1 0 IF dir=0 THEN b<=a; 1 0 0 1 0 0 ELSIF dir=1 THEN a<=b; 1 1 1 0 0 0 ENDIF; END IF ; END PROCESS ;END ar ;功能為：24譯碼器.4分2 請(qǐng)說(shuō)明下段程序的功能，寫出真值表，并畫出輸入輸出波形。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY aaa IS POR

3、T( reset,clk: IN STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset) BEGIN IF (reset='0') THEN q<="000" ELSIF (clk'event AND clk='1') THEN IF (q=5) THEN q<="000" ELSE q<=q+1; END IF; END IF; END

4、 PROCESS;END bd;功能為：帶進(jìn)位借位的4位加/減法器。.3分輸入輸出波形圖如下：7分ma3.0b3.0c3.0d1.試用VHDL語(yǔ)言編程實(shí)現(xiàn)74LS273芯片的功能。LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYls273IS1PORT(clr,clk:INstd_logic; d:INstd_logic_vector(7DOWNTO 0 );q:OUTstd_logic_vector(7 DOWNTO 0 );4);ENDls273; ARCHITECTURElock8OFls273IS1BEGINPROCESS ( clk )

5、1BEGINIF (CLR=0)THENq<=”00000000” ;2 ELSEIF (clkevent AND clk=1) THEN q<=d; 3ELSEIF ( clk=0 ) THEN q<=q; 1END IF;ENDPROCESS;ENDlock8;3. 請(qǐng)用VHDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)狀態(tài)向量發(fā)生器。LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYstasIS1PORT(cp, rst:INstd_logic; p:BUFFERstd_logic_vector(7 DOWNTO 0 );2);ENDstas; AR

6、CHITECTUREarstasOFstasIS1BEGINPROCESS (cp )1BEGINIF(rst=”0”) THENp<=”00000000”;1ELSEIF (cpevent AND cp=1 )1WITHpSELECTp<=”10101010”WHEN“00000000”;”01010101”WHEN“10101010”;”00001111”WHEN“01010101”;”11110000”WHEN“00001111”;”11111111”WHEN“11110000”;”00000000”WHEN“11111111”;”00000000”WHENOTHERS; 6

7、END IFENDPROCESS;ENDarstas;1. 閱讀下段程序，畫出該電路的真值表，并詳細(xì)說(shuō)明該電路的功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ab_8 IS PORT( a, b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); ahb, alb, aeb: OUT STD_LOGIC);END ab_8;ARCHITECTURE bd OF ab_8 IS BEGIN PROCESS(a,b) BEGIN IF a>b THEN a

8、hb<=1; alb<=0; aeb<=0; ELSIF a<b THEN ahb<=0; alb<=1; aeb<=0; ELSE ahb<=0; alb<=0; aeb<=1; END IF; END PROCESS;END bd;1.（1）真值表如下：(5)輸 入輸 出a、bahbalbaeba>b100a<b010a=b001（2）該電路是一個(gè)8位兩輸入比較器，（2）a、b是兩個(gè)8位輸入端；（1）ahb、alb和aeb為比較結(jié)果輸出端，某種比較結(jié)果為真時(shí)，相應(yīng)的輸出端為“1”，其余端輸出為“0”。（2）1. 試用V

9、HDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)2-4譯碼器，其真表如下：輸入端輸出端enselecty0XX“1111”100“1110”101“1101”110“1011”111“0111” 2-4譯碼器碼參考程序如下：（答案不唯一，用case語(yǔ)句、withselect語(yǔ)句都可以。）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;(1)ENTITY ym24 IS PORT( en : IN STD_LOGIC; select : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)(3);EN

10、D ym24;ARCHITECTURE bd OF ym24 IS BEGIN PROCESS(en)(1) IF (en=1) THEN y<= ”1110” WHEN select=”00” ELSE ”1101” WHEN select =”01” ELSE ”1011” WHEN select =”10” ELSE ”0111” WHEN select =”11” ELSE(4) ”1111”; ELSE y<=”1111”; END PROCESS;END bd;2. 試用VHDL語(yǔ)言設(shè)計(jì)一個(gè)六路8位總線復(fù)用器，其中A、B、C、D、E、F都是8位輸入總線，Q為8位輸出總線

11、，S為3位選擇端，其功能如下： 輸入端輸出端S2S1S0Q7Q0000Q=A001Q=B010Q=C011Q=D100Q=E101Q=F其它B=“00000000” 六路8位總線復(fù)用器參考程序：（答案不唯一）LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux6 IS(1)PORT( S : IN std_logic_vector(2 DOWNTO 0); A,B,C,D,E,F: IN std_logic_vector(7 DOWNTO 0); Q: OUT std_logic_vector(7 DOWNTO 0) );(3)END mux6

12、;ARCHITECTURE bd OF mux6 ISBEGIN PROCESS(S) BEGIN(1) CASE S IS WHEN "000"=>Q<=A; WHEN "001"=>Q<=B; WHEN "010"=>Q<=C; WHEN "011"=>Q<=D; WHEN "100"=>Q<=E; WHEN "101"=>Q<=F; WHEN OTHERS=>Q<="00000

13、000"(4) END CASE; END PROCESS;END bd;2、已知三選一電路如圖，判斷下列程序是否有錯(cuò)誤，如有則指出錯(cuò)誤所在，并給出完整程序。（10分）library ieee;use ieee.std_logic_1164.all;ENTITY MAX isport(a1,a2,a3,s0,s1:in bit; outy:out bit);end max; （2）architecture one of max iscomponent mux21a port(a,b,s:in std_logic; y:out std_logic);end component; （2）

14、signal temp std_logic; （2）begin u1:mux21a port map(a2,a3,s0,temp); （2） u2:mux21a port map(a1,temp,s1,outy); （2） end one;1. 已知電路原理圖如下，請(qǐng)用VHDL語(yǔ)言編寫其程序答：library ieee;use ieee.std_logic_1164.all;entity mux21 is port(a,b,s:in bit; y:out bit);end mux21; （4）architecture one of mux21 is single d,e:bit;begin d

15、<=a and (not)s; e<=b and s; y<=d or e;end one; 2. 設(shè)計(jì)一個(gè)帶有異步清零功能的十進(jìn)制計(jì)數(shù)器。計(jì)數(shù)器時(shí)鐘clk上升沿有效、清零端CLRN、進(jìn)位輸出co。 答：library ieee;use ieee.std_logic_1164.all;entity counter10 isport(clk,CLRN:in std_logic; dout:out integer range 0 to 9);end counter10; （5）architecture behav of counter10 ISbeginprocess(clk)v

16、ariable cnt:integer range 0 to 9; （3）beginIF CLRN='0' THENCNT:=0;ELSIF clk='1'and clk'event thenif cnt=9 thencnt:=0;elsecnt:=cnt+1;end if;end if;dout<=cnt;end process;end behav; （7）31）用VHDL語(yǔ)言編寫半加器和或門器件的程序，如圖所示： 答 ：半加器程序：library ieee;use ieee.std_logic_1164.all;entity h_adder i

17、sport(a,b:in std_logic; co,so:out std_logic);end h_adder; （2）architecture one of h_adder isbegin so<=not(a xor(not b); co<=a and b;end one; （3）或門程序：library ieee;use ieee.std_logic_1164.all;entity or2a is port(a,b:in std_logic; c:out std_logic);end or2a; （2）architecture one of or2a isbeginc<

18、=a or b;end one; 2）在上道題目的基礎(chǔ)上用元件例化語(yǔ)句設(shè)計(jì)1位全加器。主程序：library ieee;use ieee.std_logic_1164.all;entity f_adder is port(ain,bin,cin:in std_logic; cout,sum:out std_logic);end entity f_adder;architecture fd1 of f_adder is component h_adder port(a,b:in std_logic; co,so:out std_logic); end component; （5） compone

19、nt or2a port(a,b:in std_logic; c:out std_logic); end component; signal d,e,f:std_logic; begin u1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2 : h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3 : or2a port map(d,f,cout);end fd1; （5）1. 試用VHDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)總線開關(guān)，其真值表如下：輸 入輸 出ensele

20、ctA0A6B0B6Y0Y60x“ZZZZZZZ”10A11B 1. 總線開關(guān)的參考程序如下：LIBRARY ieee;USE ieee.std_logic_1164.all; (1)ENTITY aaa IS PORT( en, select : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(6 DOWNTO 0 ) ; Y : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) END aaa ; (4)ARCHITECTURE ar OF aaa ISBEGIN PROCESS(en, select ) BEGIN IF en=0 TH

21、EN Y<=”ZZZZZZZ”; ELSIF en=1 THEN IF select=0 THEN Y<=A; ELSIF select=1 THEN Y<=B; END IF; END IF ; END PROCESS ;END ar ; (5)2. 試用VHDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)M10計(jì)數(shù)器，要求該計(jì)數(shù)器有一個(gè)時(shí)鐘輸入端clk，一個(gè)復(fù)位端rst（低電平復(fù)位），一個(gè)使能端en（高電平時(shí)允許計(jì)數(shù)），一個(gè)“計(jì)數(shù)到”輸出端cout，一個(gè)4位二進(jìn)制當(dāng)前計(jì)數(shù)值輸出口q；cout端僅當(dāng)計(jì)數(shù)滿的一個(gè)時(shí)鐘周期輸出高電平，其余時(shí)刻全保持低電平。2. M10計(jì)數(shù)器參考程序：LIBRARY iee

22、e; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all; （1）ENTITY aaa IS PORT(clk, rst, en : IN STD_LOGIC; cout: OUT STD_LOGIC; q: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END aaa; (4)ARCHITECTURE bd OF aaa IS BEGIN PROCESS(clk,reset,en) BEGIN IF (rst='0') THE

23、N q<="0000" ELSIF (clk'event AND clk='1') THEN IF en=1 THEN IF (q=9) THEN q<="0000" ELSE q<=q+1; END IF; END IF; END IF; END PROCESS;END bd; (10)3請(qǐng)用VHDL語(yǔ)言編程，用一個(gè)狀態(tài)機(jī)模型實(shí)現(xiàn)一個(gè)七段碼LED字符發(fā)生器。該電路有一個(gè)復(fù)位輸入端RST，一個(gè)時(shí)鐘輸入端CP，一組七段碼輸出端ag。在LED上七個(gè)段的排列位置如圖所示。該電路的功能為，當(dāng)復(fù)位輸入端RST為低電平時(shí)，輸

24、出端口輸出全零，無(wú)顯示；當(dāng)RST為高電平時(shí)，在時(shí)鐘信號(hào)CP的每個(gè)上升沿，輸出端依次輪流輸出5個(gè)字符“HAPPY”的七段碼（共陰極接法），周而復(fù)始。 3. 用VHDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)LED字符發(fā)生器參考程序：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY genc IS(1) PORT( rst, cp: IN STD_LOGIC; a,b,c,d,e,f,g: OUT STD_LOGIC );(1)END genc;ARCHITECTURE aa OF genc IS TYPE state IS(s0,s1, s2, s3, s4, s5 );

25、SIGNAL pstate: state; SIGNAL dout: STD_LOGIC_VECTOR(6 DOWNTO 0 ); （2）BEGIN pr1: PROCESS(cp, rst,) BEGIN IF rst='0' THEN pstate <=s0; ELSIF （cp'event AND cp='0' ） THEN CASE pstate IS WHEN s0=> pstate <=s1;WHEN s1=> pstate <=s2; WHEN s2=> pstate <=s3; WHEN s3=&

26、gt; pstate <=s4; WHEN s4=> pstate <=s5; WHEN s5=> pstate <=s1;WHEN OTHERS=> pstate <=s0; END CASE;END IF; END PROCESS; （5） pr2: PROCESS(pstate) BEGIN CASE state IS WHEN s0 => dout<="0000000" -無(wú)顯示W(wǎng)HEN s1 => dout<="0110111" -“H” WHEN s2 => dout&l

27、t;="1110111" -“A” WHEN s3 => dout<="1100111" -“P” WHEN s4 => dout<="1100111" -“P” WHEN s5 => dout<="0111011" -“Y” WHEN OTHERS=> dout<="0000000"-無(wú)顯示 END CASE; END PROCESS; （5） a<=dout(6); b<=dout(5); c<=dout(4); d<=

28、dout(3); e<=dout(2); f<=dout(1); g<=dout(0);END aa; （1）2試用VHDL語(yǔ)言和進(jìn)程語(yǔ)句，編程實(shí)現(xiàn)一個(gè)3-8譯碼器。該譯碼器的功能為，當(dāng)使能信號(hào)EN為低電平時(shí)，輸出端Y7Y0全為高電平（沒(méi)有輸出端被選中）；當(dāng)EN為高電平時(shí)，每一種ABC的輸入狀態(tài)組合能惟一地選中一路輸出（被選中的端輸出低電平）。真值表如下：輸 入輸 出ABCENY7Y6Y5Y4Y3Y2Y1Y00001111111100011111111010101111110110111111101111001111011111011110111111101101111111

29、11101111111×××011111111 LIBRARY ieee; USEieee.std_logic_1164.ALL;2ENTITYym38IS1PORT(a, b, c, en:INstd_logic; y:OUTstd_logic_vector(7 DOWNTO 0 );3);ENDym38; ARCHITECTUREarc38OFls273IS1BEGINPROCESS ( en )1SIGNALdin:std_logic_vector(7 DOWNTO 0 );1BEGINdin<=a&b&c&en; 1WITHd

30、inSELECTy<=”11111110”WHEN“0001”;”11111101”WHEN“0011”;”11111011”WHEN“0101”;”11110111”WHEN“0111”;”11101111”WHEN“1001”;”11011111”WHEN“1011”;”10111111”WHEN“1101”;”01111111”WHEN“1111”;5”11111111”WHENOTHERS;ENDPROCESS;ENDarc38;1. 試用VHDL語(yǔ)言編程實(shí)現(xiàn)一個(gè)多路開關(guān)。該電路的功能為，當(dāng)選擇端S0和S1為不同狀態(tài)組合時(shí)，如果使能信號(hào)EN為電平，輸出端X和Y分別與不同的輸入通道

31、A0B0、A1B1、A2B2和A3B3接通并保持，當(dāng)EN為低電平時(shí)，X、Y輸出為高阻態(tài)。真值表如下：輸 入輸 出S1S0ENA0B0A1B1A2B2A3B3XY001××××××××A0B0011××××××××A1B1101××××××××A2B2111××××××××A3B3

32、××0××××××××ZZ1. 多路開關(guān)的參考程序如下：LIBRARY ieee; USEieee.std_logic_1164.ALL;ENTITYmulkeyISPORT(s0,s1,en, a0,b0,a1,b1,a2,b2,a3,b3:INstd_logic; x,y:OUTstd_logic_vector(7 DOWNTO 0 );3);ENDmulkey; ARCHITECTUREarmkOFmulkeyISSIGNAL sel: std_logic_vecter (1 DOWNTO

33、 0 )BEGIN sel<=s1&s0; 2PROCESS (en )BEGINIF (en=0)THENx<=Z;y<=Z; ELSEIF (sel=”00”) THEN x<=a0 ;y<=b0; ELSEIF (sel=”01”) THEN x<=a1 ;y<=b1; ELSEIF (sel=”10”) THEN x<=a2;y<=b2; ELSEIF (sel=”11”) THEN x<=a3 ;y<=b3; END IF;ENDPROCESS;ENDarmk; 六、寫VHDL程序：（10分）1. 設(shè)計(jì)10進(jìn)制

34、加法計(jì)數(shù)器，要求含異步清0和同步時(shí)鐘使能。注意：時(shí)鐘信號(hào)命名為CLK，使能信號(hào)為EN，清零信號(hào)為RST，計(jì)數(shù)輸出為CQ。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 IS PORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10;ARCHITECTURE behav OF CNT10 ISBEGIN PROCESS(C

35、LK, RST, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = '1' THEN CQI := (OTHERS =>'0') ; -計(jì)數(shù)器異步復(fù)位 ELSIF CLK'EVENT AND CLK='1' THEN -檢測(cè)時(shí)鐘上升沿 IF EN = '1' THEN -檢測(cè)是否允許計(jì)數(shù)（同步使能） IF CQI < 9 THEN CQI := CQI + 1; -允許計(jì)數(shù), 檢測(cè)是否小于9 ELSE CQI := (OTHERS =

36、>'0'); -大于9，計(jì)數(shù)值清零 END IF; END IF; END IF; IF CQI = 9 THEN COUT <= '1' -計(jì)數(shù)大于9，輸出進(jìn)位信號(hào) ELSE COUT <= '0' END IF; CQ <= CQI; -將計(jì)數(shù)值向端口輸出 END PROCESS;END behav; 2.試描述一個(gè)帶進(jìn)位輸入、輸出的8位全加器端口：A、B為加數(shù)，CIN為進(jìn)位輸入，S為加和，COUT為進(jìn)位輸出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 I

37、SPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END ADDER8;ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0);BEGINTS <= (0 & A) + (0 & B) + CIN;S <= TS(7 DOWNTO 0);COUT <= TS(8);EN

38、D ONE;七、VHDL程序設(shè)計(jì)：（20分）設(shè)計(jì)一數(shù)據(jù)選擇器MUX,其系統(tǒng)模塊圖和功能表如下圖所示。試采用下面三種方式中的兩種來(lái)描述該數(shù)據(jù)選擇器MUX的結(jié)構(gòu)體。(a) 用if語(yǔ)句。 (b) 用case 語(yǔ)句。 (c) 用when else 語(yǔ)句。Library ieee;Use ieee.std_logic_1164.all;Entity mymux isPort (sel : in std_logic_vector(1 downto 0);- 選擇信號(hào)輸入Ain, Bin : in std_logic_vector(1 downto 0);- 數(shù)據(jù)輸入Cout : out std_logic

39、_vector(1 downto 0) );End mymux;Architecture one of mymux isBeginProcess (sel, ain, bin)BeginIf sel = “00” then cout <= ain and bin; Elsif sel = “01” then cout <= ain xor bin;Elsif sel = “10” then cout <= not ain;Else cout <= not bin;End if;End process;End one;Architecture two of mymux i

40、sBeginProcess (sel, ain, bin)BeginCase sel iswhen “00” => cout <= ain and bin; when “01” => cout <= ain xor bin;when “10” => cout <= not ain;when others => cout <= not bin;End case;End process;End two;Architecture three of mymux isBeginCout <= ain and bin when sel = “00” e

41、lseAin xor bin when sel = “01” elseNot ain when sel = “10” else not bin;End three;設(shè)計(jì)一個(gè)7段數(shù)碼顯示譯碼器，并逐行進(jìn)行解釋LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DECL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ; END ; ARCHITECTURE one OF DECL7S IS BEGIN PROC

42、ESS( A ) BEGIN CASE A IS WHEN "0000" => LED7S <= "0111111" ; WHEN "0001" => LED7S <= "0000110" ; WHEN "0010" => LED7S <= "1011011" ; WHEN "0011" => LED7S <= "1001111" ; WHEN "0100" =>

43、 LED7S <= "1100110" ; WHEN "0101" => LED7S <= "1101101" ; WHEN "0110" => LED7S <= "1111101" ; WHEN "0111" => LED7S <= "0000111" ; WHEN "1000" => LED7S <= "1111111" ; WHEN "1001&q

44、uot; => LED7S <= "1101111" ; WHEN "1010" => LED7S <= "1110111" ; WHEN "1011" => LED7S <= "1111100" ; WHEN "1100" => LED7S <= "0111001" ; WHEN "1101" => LED7S <= "1011110" ; WHEN &q

45、uot;1110" => LED7S <= "1111001" ; WHEN "1111" => LED7S <= "1110001" ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; 關(guān)于數(shù)據(jù)選擇器餓設(shè)計(jì)1、4選1多路選擇器的IF語(yǔ)句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_1 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_1;architecture archi of multip