第06章系統(tǒng)控制(時(shí)鐘振蕩器看門狗PLL)

1、第第6章章 時(shí)鐘與系統(tǒng)時(shí)鐘與系統(tǒng)控制控制1 時(shí)鐘和系統(tǒng)控制時(shí)鐘和系統(tǒng)控制2 振蕩器和鎖相環(huán)振蕩器和鎖相環(huán)3 看門狗電路看門狗電路4 低功耗模塊低功耗模塊本講內(nèi)容本講內(nèi)容1 時(shí)鐘和系統(tǒng)控制時(shí)鐘和系統(tǒng)控制2 振蕩器和鎖相環(huán)振蕩器和鎖相環(huán)3 看門狗電路看門狗電路4 低功耗模塊低功耗模塊時(shí)鐘與系統(tǒng)時(shí)鐘與系統(tǒng)控制控制時(shí)時(shí)鐘鐘與與系系統(tǒng)統(tǒng)控控制制 框框圖圖時(shí)鐘與時(shí)鐘與系統(tǒng)控制系統(tǒng)控制的寄存器的寄存器外設(shè)時(shí)鐘控制寄存器外設(shè)時(shí)鐘控制寄存器PCLKCR 701ChreservedreservedEVAENCLKEVBENCLKreservedADCENCLKreservedreservedECANENCLKSP

2、IAENCLKSCIBENCLKreservedSCIAENCLKMCBSPENCLKreservedreservedHSPCLKLSPCLK高高/低速外設(shè)時(shí)鐘預(yù)定標(biāo)寄存器低速外設(shè)時(shí)鐘預(yù)定標(biāo)寄存器HISPCP 701Ah / LOSPCP 701Bh0215 - 3HSPCLKreservedH/LSPCLK2 H/LSPCLK1 H/LSPCLK0 Peripheral Clock Frequency 0 0 0 SYSCLKOUT / 1 0 0 1 SYSCLKOUT / 2 (default HISPCP) 0 1 0 SYSCLKOUT / 4 (default LOSPCP) 0

3、1 1 SYSCLKOUT / 6 1 0 0 SYSCLKOUT / 8 1 0 1 SYSCLKOUT / 10 1 1 0 SYSCLKOUT / 12 1 1 1 SYSCLKOUT / 14 0215 - 3LSPCLKreserved1 時(shí)鐘和系統(tǒng)控制時(shí)鐘和系統(tǒng)控制2 振蕩器和鎖相環(huán)振蕩器和鎖相環(huán)3 看門狗電路看門狗電路4 低功耗模塊低功耗模塊時(shí)鐘與系統(tǒng)時(shí)鐘與系統(tǒng)控制控制C28x Osc / PLL 時(shí)鐘模塊時(shí)鐘模塊PLLCR 7021hDIV3 DIV2 DIV1 DIV0 Clock Frequency (CLKIN) 0 0 0 0 OSCCLK x 1 / 2 (no PL

4、L) 0 0 0 1 OSCCLK x 1 / 2 0 0 1 0 OSCCLK x 2 / 2 0 0 1 1 OSCCLK x 3 / 2 0 1 0 0 OSCCLK x 4 / 2 0 1 0 1 OSCCLK x 5 / 2 0 1 1 0 OSCCLK x 6 / 2 0 1 1 1 OSCCLK x 7 / 2 1 0 0 0 OSCCLK x 8 / 2 1 0 0 1 OSCCLK x 9 / 2 1 0 1 0 OSCCLK x 10 / 2PLLCRbits 15:4reservedcrystalPLLClock Module4-bit PLL SelectX1 /CLK

5、INX2XTAL OSCWatchdogModule/2PLLCLKOSCCLKC28xCoreCLKINMUXXF_XPLLDIS10SYSCLKOUTHISPCPLOSPCPHSPCLKLSPCLK1、PLL旁路旁路2、PLL使能使能1 時(shí)鐘和系統(tǒng)控制時(shí)鐘和系統(tǒng)控制2 振蕩器和鎖相環(huán)振蕩器和鎖相環(huán)3 看門狗電路看門狗電路4 低功耗模塊低功耗模塊時(shí)鐘與系統(tǒng)時(shí)鐘與系統(tǒng)控制控制看門狗模塊看門狗模塊u如果CPU崩潰，則復(fù)位系統(tǒng)l看門狗計(jì)數(shù)器獨(dú)立于CPUl如果計(jì)數(shù)器溢出則復(fù)位或中斷被觸發(fā)l為防止計(jì)數(shù)器溢出，CPU必須周期性的向看門狗WDKEY寄存器寫入0X55+0XAA序列u在 復(fù)位之后 (10 M

6、外部時(shí)鐘)3ms之內(nèi)看門狗必須被啟用或者禁止（對不對？）看門狗模塊看門狗模塊6 - BitFree -RunningCounterCLR/2/4/8/16/32/64OSCCLKSystemReset1011000110100010001111108 - Bit WatchdogCounterCLROne-CycleDelayWatchdogReset KeyRegister55 + AADetectorGood KeyBad Key1 0 1 /33WDCR . 2 - 0WDCR . 6WDPSWDDISWDCR . 7WDFLAGWDCNTR . 7 - 0WDKEY . 7 - 0WD

7、CR . 5 - 3 WDCHK 2-0Bad WDCR Key/512OutputPulseWDRSTWDINTSCSR .1WDENINTSCSR . 0WDOVERRIDE看門狗看門狗 控制寄存器控制寄存器 WDCR 7029hWDFLAGWDDIS76543210WDCHK1 WDCHK0WDPS2WDPS1WDPS0WDCHK2Logic Check BitsWrite as 101 or reset immediately triggeredWD PrescaleSelection BitsWatchdog Disable Bit(Functions only if WD OVER

8、RIDEbit in SCSR is equal to 1)reserved15 - 8WD Flag BitGets set when the WD causes a reset Writing a 1 clears this bit Writing a 0 has no effect看門狗看門狗 復(fù)位密鑰寄存器復(fù)位密鑰寄存器 WDKEY 7025hu允許寫入的數(shù)值:55h 在AAH之后的寫入55使能計(jì)數(shù)器AAh 如果復(fù)位使能則計(jì)數(shù)器清零u寫入其他任何值將復(fù)位CPU或觸發(fā)WDINT中斷？reservedD776543210D6D5D4D3D2D1D015 - 8WDKEY 寫操作寫操作Seq

9、uentialStep1234567891011Value Writtento WDKEYAAhAAh55h55h55hAAhAAh55hAAh55h23hResultNo actionNo actionWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter is resetNo actionWD counter enabled for reset on

10、next AAh writeWD counter is resetWD counter enabled for reset on next AAh writeCPU reset triggered due to improper write value系統(tǒng)控制和狀態(tài)寄存器系統(tǒng)控制和狀態(tài)寄存器SCSR 7022hWD Override (protect bit)After RESET - bit gives user ability to disable WD by setting WDDIS bit=1 in WDCR clear only bit and defaults to 1 afte

11、r reset 0 = protects WD from being disabled by s/w bit cannot be set to 1 by s/w (clear-only by writing 1) 1 = (default value) allows WD to be disabled using WDDIS bit in WDCR once cleared, bit cannot set to 1 by s/w01215 - 3WDOVERRIDEWDENINTWDINTSreservedWD Enable InterruptWD Interrupt Status(read

12、only)0 = active1 = not active0 = WD generates a DSP reset1 = WD generates a WDINT interrupt1 時(shí)鐘和系統(tǒng)控制時(shí)鐘和系統(tǒng)控制2 振蕩器和鎖相環(huán)振蕩器和鎖相環(huán)3 看門狗電路看門狗電路4 低功耗模塊低功耗模塊時(shí)鐘與系統(tǒng)時(shí)鐘與系統(tǒng)控制控制低功耗模式低功耗模式Low PowerModeCPU LogicClockPeripheralLogic ClockWatchdogClockPLL /OSCNormal RunIDLESTANDBYHALTonoffoffoffononoffoffonononoffonono

13、noff低功耗方式控制低功耗方式控制0寄存器寄存器LPMCR0 701Eh017 - 215 - 8LPM0LPM1QUALSTDBYreservedLow Power Mode Entering1. Set LPM bits2. Enable desired exit interrupt(s)3. Execute IDLE instruction4. The Power down sequence of the hardware depends on LP modeLow Power Mode Selection00 = Idle01 = Standby1x = HaltQualify be

14、fore wakingfrom STANDBY mode000000 = 2 OSCCLKs000001 = 3 OSCCLKs111111 = 65 OSCCLKS.低功耗模式控制低功耗模式控制1寄存器寄存器LPMCR1 701FhWake device from STANDBY mode0 = disable1 = enable0WDINTSCIRXBC2TRIPC5TRIPT3CTRIP123456789101112131415XINT1XNMIT2CTRIP T1CTRIPC3TRIPT4CTRIPC4TRIPC1TRIPC6TRIPSCIRXACANRXAIDLESTANDBYHALTRESETyesyesyesExternalorWake upInterruptsyesyesnoyesnonoExitInterruptLow PowerModeEnabledPeripheralInterruptsNote: External o