M24128,M24256-存儲(chǔ)芯片手冊(cè)免費(fèi)下載

1、M24256M24128256/128 Kbit Serial I²C Bus EEPROMWithout Chip Enable Liness sCompatible with I2C Extended AddressingTwo Wire I2C Serial InterfaceSupports 400kHz ProtocolSingle Supply Voltage:4.5V to 5.5V for M24xxx2.5V to 5.5V for M24xxx-Wss s s s s s s sHardware Write ControlBYTE and PAGE WRITE (

2、up to 64 BytesRANDOM and SEQUENTIAL READ ModesSelf-Timed Programming CycleAutomatic Address IncrementingEnhanced ESD/Latch-Up BehaviorMore than 100,000 Erase/Write CyclesMore than 40 Year Data RetentionDESCRIPTIONThese I2C-compatible electrically erasable pro-grammable memory (EEPROM devices are org

3、a-nized as 32Kx8 bits (M24256 and 16Kx8 bits(M24128, and operate down to 2.5V (for the -Wversion of each device.The M24256B, M24128B and M24256A are alsoavailable, and offer the extra functionality of thechip enable inputs. Please see the separate datasheets for details of these products.The M24256

4、and M24128 are available in PlasticDual-in-Line and Plastic Small Outline packages.These memory devices are compatible with theI 2C extended memory standard. This is a two wire Table 1. Signal NamesSDA SCL V CC V SSSerial Data/Address Input/Output Serial ClockWrite ControlSupply VoltageGround June 2

5、0011/17M24256, M24128 serial interface that uses a bi-directional data busand serial clock. The memory carries a built-in 4-bit unique Device Type Identifier code (1010 inaccordance with the I2C bus definition.The memory behaves as a slave device in the I2C protocol, with all memory operations synch

6、ronizedby the serial clock. Read and Write operations areinitiated by a START condition, generated by thebus master. The START condition is followed by aTable 3, terminated by an acknowledge bit.When writing data to the memory, the memory in-serts an acknowledge bit during the 9th bit time,following

7、 the bus masters 8-bit transmission.When data is read by the bus master, the busmaster acknowledges the receipt of the data bytein the same way. Data transfers are terminated bya STOP condition after an Ack for WRITE, and af-ter a NoAck for READ.Table 2. Absolute Maximum Ratings 1Symbol T A T STG T

8、LEAD V IO V CC V ESDParameterAmbient Operating TemperatureStorage TemperatureLead Temperature during SolderingInput or Output rangeSupply VoltagePower On Reset: VCC Lock-Out Write ProtectIn order to prevent data corruption and inadvertentwrite operations during power up, a Power On Re-set (POR circu

9、it is included. The internal reset isheld active until the VCC voltage has reached thePOR threshold value, and all operations are dis-abled the device will not respond to any com-mand. In the same way, when VCC drops from theoperating voltage, below the POR threshold value,all operations are disable

10、d and the device will notrespond to any command. A stable and valid VCC must be applied before applying any logic signal.SIGNAL DESCRIPTIONSerial Clock (SCLThe SCL input pin is used to strobe all data in andout of the memory. In applications where this lineis used by slaves to synchronize the bus to

11、 a slow- Value 40 to 12565 to 150PDIP: 10 secondsSO: 20 seconds (max 2Unit °C°C°CV V VElectrostatic Discharge Voltage (Human Body model 3Note:1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” maycause permanent

12、damage to the device. These are stress ratings only, and operation of the device at these or any other conditionsabove those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability. R

13、efer also to the ST SURE Program and other relevant quality documents.2. IPC/JEDEC J-STD-020A3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 , R2=500 2/17M24256, M24128er clock, the master must have an open drain out-put, and a pull-up resistor must be connected fromthe SCL line to VCC . (Figure 3 indi

14、cates how thevalue of the pull-up resistor can be calculated. Inmost applications, though, this method of synchro-nization is not employed, and so the pull-up resis-tor is not necessary, provided that the master hasa push-pull (rather than open drain output.Serial Data (SDAThe SDA pin is bi-directio

15、nal, and is used to trans-fer data in or out of the memory. It is an open drainoutput that may be wire-ORed with other opendrain or open collector signals on the bus. A pullup resistor must be connected from the SDA busto VCC . (Figure 3 indicates how the value of thepull-up resistor can be calculat

16、ed.Write Control (WCprotecting the entire contents of the memory frominadvertent erase/write. The Write Control signal isIL IH write instructions to the entire memory area. WhenV IL , and write operations are allowed.are acknowledged, Data bytes are not acknowl-edged.Please see the Application Note

17、AN404 for a moredetailed description of the Write Control feature.DEVICE OPERATIONThe memory device supports the I2C protocol.This is summarized in Figure 4, and is comparedwith other serial bus protocols in Application NoteAN1001. Any device that sends data on to the busis defined to be a transmitt

18、er, and any device thatreads the data to be a receiver. The device thatcontrols the data transfer is known as the master,and the other as the slave. A data transfer can onlybe initiated by the master, which will also providethe serial clock for synchronization. The memorydevice is always a slave dev

19、ice in all communica-tion.Start ConditionSTART is identified by a high to low transition ofthe SDA line while the clock, SCL, is stable in thehigh state. A START condition must precede anydata transfer command. The memory device con-tinuously monitors (except during a programmingcycle the SDA and SC

20、L lines for a START condi-tion, and will not respond unless one is given.Stop ConditionSTOP is identified by a low to high transition of theSDA line while the clock SCL is stable in the highstate. A STOP condition terminates communica-tion between the memory device and the bus mas-ter. A STOP condit

21、ion at the end of a Readcommand, after (and only after a NoAck, forcesthe memory device into its standby state. A STOPcondition at the end of a Write command triggersthe internal EEPROM write cycle.Acknowledge Bit (ACKAn acknowledge signal is used to indicate a suc-cessful byte transfer. The bus tra

22、nsmitter, whetherit be master or slave, releases the SDA bus aftersending eight bits of data. During the 9th clockpulse period, the receiver pulls the SDA bus low toacknowledge the receipt of the eight data bits.Data InputDuring data input, the memory device samples theSDA bus signal on the rising e

23、dge of the clock,SCL. For correct device operation, the SDA signal 23/17M24256, M241282must be stable during the clock low-to-high transi-tion, and the data must change only when the SCLline is low.Memory AddressingTo start communication between the bus masterand the slave memory, the master must in

24、itiate aSTART condition. Following this, the master sendsthe 8-bit byte, shown in Table 3, on the SDA busline (most significant bit first. This consists of thether subdivided into: a 4-bit Device Type Identifier,and a 3-bit Chip Enable “Address” (0, 0, 0.To address the memory array, the 4-bit Device

25、Type Identifier is 1010b.The 8th and 0 for write operations. If a match occurs onthe Device Select Code, the corresponding mem-ory gives an acknowledgment on the SDA bus dur-ing the 9th bit time. If the memory does not matchthe Device Select Code, it deselects itself from thebus, and goes into stand

26、-by mode. Table 3. Device Select Code 1Device Type Identifierb7Device Select Code1b60b51b40b30Chip Enableb20b10b0Note:1. The most significant bit, b7, is sent first.4/17M24256, M24128Table 4. Operating ModesModeCurrent Address ReadRandom Address ReadSequential ReadByte WritePage WriteNote:1. X = IH

27、IL .1011001X X X X V IL V ILData Bytes11 11Initial SequenceSimilar to Current or Random Address Read 64 There are two modes both for read and write.These are summarized in Table 4 and describedlater. A communication between the master andthe slave is ended with a STOP condition.Each data byte in the

28、 memory has a 16-bit (twobyte wide address. The Most Significant Byte (Ta-ble 5 is sent first, followed by the Least significantByte (Table 6. Bits b15 to b0 form the address ofthe byte in memory. Bit b15 is treated as a DontCare bit on the M24256 memory. Bits b15 and b14are treated as Dont Care bit

29、s on the M24128memory.5/17M24256, M24128Table 5. Most Significant Byteb15b14b13b12b11b10b9b8Note:1. b15 is treated as Dont Care on the M24256 series.b15 and b14 are Dont Care on the M24128 series.Table 6. Least Significant Byteb7b6b5b4b3b2b1b0Write OperationsFollowing a START condition the master se

30、nds ashown in Table 4. The memory acknowledges this,and waits for two address bytes. The memory re-sponds to each address byte with an acknowledgebit, and then waits for the data byte.input pin is taken high. Any write command withcondition until the end of the two address byteswill not modify the m

31、emory contents, and the ac-companying data bytes will not be acknowledged,as shown in Figure 5.Byte WriteIn the Byte Write mode, after the Device SelectCode and the address bytes, the master sendsone data byte. If the addressed location is writea NoAck, and the location is not modified. If, in-Figur

32、e 6, the memory replies with an Ack. Themaster terminates the transfer by generating aSTOP condition.Page WriteThe Page Write mode allows up to 64 bytes to bewritten in a single write cycle, provided that theyare all located in the same row in the memory:that is the most significant memory address b

33、its(b14-b6 for the M24256 and b13-b6 for theM24128 are the same. If more bytes are sent than6/17 M24256, M24128will fit up to the end of the row, a condition knownas roll-over occurs. Data starts to become over-written (in a way not formally specified in this datasheet.The master sends from one up t

34、o 64 bytes of data,each of which is acknowledged by the memory iftents of the addressed memory location are notmodified, and each data byte is followed by aNoAck. After each byte is transferred, the internalbyte address counter (the 6 least significant bitsonly is incremented. The transfer is termin

35、ated bythe master generating a STOP condition.When the master generates a STOP condition im-mediately after the Ack bit (in the “10th bit” timeslot, either at the end of a byte write or a pagewrite, the internal memory write cycle is triggered.A STOP condition at any other time does not trig-ger the

36、 internal write cycle. During the internal write cycle, the SDA input isdisabled internally, and the device does not re-spond to any requests.Minimizing System Delays by Polling On ACKDuring the internal write cycle, the memory discon-nects itself from the bus, and copies the data fromits internal l

37、atches to the memory cells. The maxi-mum write time (tw is shown in Table 10, but thetypical time is shorter. To make use of this, an Ackpolling sequence can be used by the master. The sequence, as shown in Figure 7, is:Initial condition: a Write is in progress.Step 1: the master issues a START cond

38、itionfollowed by a Device Select Code (the first byteof the new instruction.Step 2: if the memory is busy with the internalwrite cycle, no Ack will be returned and the mas-ter goes back to Step 1. If the memory has ter-7/17M24256, M24128minated the internal write cycle, it responds withan Ack, indic

39、ating that the memory is ready toreceive the second part of the next instruction(the first byte of this instruction having been sentduring Step 1.Read OperationsRead operations are performed independently ofRandom Address ReadA dummy write is performed to load the addressinto the address counter, as

40、 shown in Figure 8.Then, without sending a STOP condition, the mas-ter sends another START condition, and repeats 8/17the Device Select Code, with the RW bit set to 1.The memory acknowledges this, and outputs thecontents of the addressed byte. The master mustnot acknowledge the byte output, and term

41、inatesthe transfer with a STOP condition.Current Address ReadThe device has an internal address counter whichis incremented each time a byte is read. For theCurrent Address Read mode, following a STARTcondition, the master sends a Device Select Codeedges this, and outputs the byte addressed by thein

42、ternal address counter. The counter is then in-M24256, M24128Table 7. DC CharacteristicsSymbol I LI I LO I CC ParameterInput Leakage Current(SCL, SDAOutput Leakage CurrentSupply CurrentSupply Current (Stand-byInput Low Voltage (SCL, SDAInput High Voltage (SCL, SDAOutput Low VoltageI OL = 3mA, VCC =

43、5V-W series:Test Condition0V V IN VCC0V VOUT VCC, SDA in Hi-ZV CC =5V, fc =400kHz (rise/fall time < 30ns-W series:V CC =2.5V, fc =400kHz (rise/fall time < 30nsV IN = VSS or V CC , VCC = 5V-W series:0.30.7V CC 0.30.7V CC Min.Unit µAµAmA mA µAµAV V V V V VI CC1V IL V IH V IL

44、V IH V OLTable 8. Input Parameters1 (TA = 25 °C, f = 400 kHzSymbol C IN C IN Z L Z H t NSParameterInput Capacitance (SDAInput Capacitance (other pinsLow Pass Filter Input Time Constant (SCL and SDA5500100Test ConditionMin.Max. 86Unit pF pF k k nsNote:1. Sampled only, not 100% tested.Table 9. AC

45、 Measurement ConditionsInput Rise and Fall TimesInput Pulse VoltagesInput and Output Timing Reference Voltages9/17M24256, M24128Table 10. AC CharacteristicsM24256 / M24128SymbolAlt.ParameterV CC =4.5 to 5.5V T A =40 to 85°CMint CH1CH2t CL1CL2t DH1DH2 2t DL1DL2 2t CHDX 1t CHCL t DLCL t CLDX t CL

46、CH t DXCX t CHDH t DHDL t CLQV 3t CLQX f C t Wt R t F t R t F t SU:STA t HIGH t HD:STA t HD:DATt LOW t SU:DAT t SU:STOt BUF t AA t DH f SCL t WRClock Rise TimeClock Fall TimeSDA Rise TimeSDA Fall TimeClock High to Input TransitionClock Pulse Width HighInput Low to Clock Low (STARTClock Low to Input

47、TransitionClock Pulse Width LowInput Transition to Clock TransitionClock High to Input High (STOPInput High to Input Low (Bus FreeClock Low to Data Out ValidData Out Hold Time After Clock LowClock FrequencyWrite Time40010900Max 30030030030040010900V CC =2.5 to 5.5V T A =40 to 85°CMinMax 3003003

48、00300ns ns ns ns ns ns ns µsµsns ns µsns ns kHz ms UnitNote:1. For a reSTART condition, or following a write cycle.2. Sampled only, not 100% tested.3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.cremented.

49、The master terminates the transferwith a STOP condition, as shown in Figure 8, with-out acknowledging the byte output.Sequential ReadThis mode can be initiated with either a CurrentAddress Read or a Random Address Read. Themaster does acknowledge the data byte output inthis case, and the memory cont

50、inues to output thenext byte in sequence. To terminate the stream ofbytes, the master must not acknowledge the lastbyte output, and must generate a STOP condition.The output data comes from consecutive address-es, with the internal address counter automaticallyincremented after each byte output. Aft

51、er the lastmemory address, the address counter rolls-overand the memory continues to output data frommemory address 00h.Acknowledge in Read ModeIn all read modes, the memory waits, after eachbyte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA linelow during

52、this time, the memory terminates thedata transfer and switches to its stand-by state.10/17M24256, M24128 11/17M24256, M24128Table 11. Ordering Information SchemeExample:M24256 WMN1TMemory Capacity256128256 Kbit (32K x 8128 Kbit (16K x 8TOptionTape and Reel PackingTemperature Range65Operating Voltage

53、blank 14.5V to 5.5V WBNPackagePDIP8 (0.25 mm frame40 °C to 85 °C20 °C to 85 °CMN 2SO8 (150 mil widthMW 3SO8 (200 mil widthNote:1. Available only on request.2. Available for M24128 only.3. Available for M24256 only.ORDERING INFORMATIONDevices are shipped from the factory with them

54、emory content set at all 1s (FFh.The notation used for the device number is asshown in Table 11. For a list of available options(speed, package, etc. or for further information onany aspect of this device, please contact yournearest ST Sales Office.12/17M24256, M24128 PDIP8 8 pin Plastic DIP, 0.25mm

55、 lead frameSymb. A A1A2b b2c D E E1e eA eB L0.382.920.361.140.209.027.626.10mmTyp.Min.0.0150.1150.0140.0450.0080.3550.3000.240Typ.inches Min.13/17M24256, M24128SO8 narrow 8 lead Plastic Small Outline, 150 mils body widthSymb. A A1B C D E e H h L N CPmmTyp.Min. 1.350.100.330.194.803.805.800.250.400°80.10Max. 1.750.250.510.255.004.006.200.500.908°0.050Typ.inches Min. 0.0530.0040.0130.0070.1890.1500.2280.0100.0160°80.004Max. 0.0690.0100.0200.0100.1970.1570.2440.0200.0358