數(shù)電實(shí)驗(yàn)實(shí)驗(yàn)報(bào)告

1、 數(shù)電實(shí)驗(yàn)實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)題目：ALU算數(shù)邏輯單元設(shè)計(jì)姓名：黎俁珩、戴超男班級(jí)：2010001010學(xué)號(hào)：2010001010001、2010021010013指導(dǎo)老師：陳學(xué)英、李書洋地點(diǎn)與時(shí)間：6.8科研樓A304 【摘要】： 作為計(jì)算器功能的ALU可以進(jìn)行二進(jìn)制的一些簡(jiǎn)單的運(yùn)算，例如加減乘以及左右移位，從而形成一個(gè)復(fù)合的運(yùn)算單元，這次的實(shí)驗(yàn)中，我們即基于FPGA的基礎(chǔ)上，利用ISE軟件完成ALU的設(shè)計(jì)和仿真工作。一、任務(wù)要求1.1 實(shí)驗(yàn)?zāi)康模?）熟悉用ISE軟件進(jìn)行設(shè)計(jì)的流程；（2) 掌握ALU邏輯運(yùn)算單元的電路結(jié)構(gòu)與運(yùn)算機(jī)制，掌握ALU的運(yùn)算模塊及其設(shè)計(jì)方法，編寫幾種簡(jiǎn)單的數(shù)字運(yùn)算的程序；（

2、3) 熟悉FPGA硬件平臺(tái)的基本知識(shí)；（4) 熟悉chipscope軟件測(cè)試的方法；利用VHDL語(yǔ)言，我們可以設(shè)計(jì)一個(gè)ALU邏輯運(yùn)算單元，并調(diào)用ISE軟件提供的IP core用FPGA板實(shí)現(xiàn)程序下板，并用chipscope抓點(diǎn)觀察產(chǎn)生的數(shù)字波形。設(shè)計(jì)基本原理圖如下：圖11.2 實(shí)驗(yàn)指標(biāo)1、利用Modelsin軟件編寫出ALU的代碼，根據(jù)仿真波形來(lái)驗(yàn)證代碼的正確性以及運(yùn)算的可靠性。2、利用ISE設(shè)計(jì)出ALU的頂層連線結(jié)構(gòu)與虛擬輸入輸出結(jié)構(gòu)，將VHDL下載到實(shí)驗(yàn)FPGA板上，并使用chipscope進(jìn)行電路實(shí)驗(yàn)，在軟件上觀察輸出的數(shù)字的正確性和運(yùn)算的可靠性。二、實(shí)驗(yàn)原理及方案2.1 原理描述算術(shù)邏

3、輯單元是中央處理器(CPU)的執(zhí)行單元，是所有中央處理器的核心組成部分，由"And Gate" 和"Or Gate"構(gòu)成的算術(shù)邏輯單元，主要功能是進(jìn)行二進(jìn)制的算術(shù)運(yùn)算，如加減乘(不包括整數(shù)除法)?；旧希谒鞋F(xiàn)代CPU體系結(jié)構(gòu)中，二進(jìn)制都以二補(bǔ)數(shù)的形式來(lái)表示。運(yùn)算器包括寄存器、執(zhí)行部件和控制電路3個(gè)部分。在典型的運(yùn)算器中有3個(gè)寄存器：接收并保存一個(gè)操作數(shù)的接收寄存器；保存另一個(gè)操作數(shù)和運(yùn)算結(jié)果的累加寄存器；在進(jìn)行乘、除運(yùn)算時(shí)保存乘數(shù)或商數(shù)的乘商寄存器。執(zhí)行部件包括一個(gè)加法器和各種類型的輸入輸出門電路?？刂齐娐钒凑找欢ǖ臅r(shí)間順序發(fā)出不同的控制信號(hào)，使數(shù)據(jù)

4、經(jīng)過(guò)相應(yīng)的門電路進(jìn)入寄存器或加法器，完成規(guī)定的操作。 為了減少對(duì)存儲(chǔ)器的訪問(wèn)，很多計(jì)算機(jī)的運(yùn)算器設(shè)有較多的寄存器，存放中間計(jì)算結(jié)果，以便在后面的運(yùn)算中直接用作操作數(shù)。為了提高運(yùn)算速度，某些大型計(jì)算機(jī)有多個(gè)運(yùn)算器。它們可以是不同類型的運(yùn)算器，如定點(diǎn)加法器、浮點(diǎn)加法器、乘法器等，也可以是相同類型的運(yùn)算器。2.2 實(shí)驗(yàn)方案1.加法器，減法器：使用Modelsim編譯最基礎(chǔ)的全加器，使用全加器層層構(gòu)建出4位符號(hào)數(shù)加法器和減法器，在編譯時(shí)，應(yīng)該使用符號(hào)數(shù)加減法的基本原理，在構(gòu)建加法器時(shí)遵循如下結(jié)構(gòu)圖2而當(dāng)構(gòu)建減法器時(shí)，應(yīng)該使用相似的結(jié)構(gòu)，因?yàn)闇p法即加法，只是加的數(shù)字是復(fù)數(shù)而已，因?yàn)榭紤]到符號(hào)位運(yùn)算，故而

5、采用取補(bǔ)碼運(yùn)算，最后只需要在FA1的進(jìn)位位輸入1，既可完成減法運(yùn)算。2.乘法器：乘法器因?yàn)橹灰鬅o(wú)符號(hào)運(yùn)算，因此采用徒手乘法的邏輯算法，將一層一層的乘法運(yùn)算逐位相加，最后可以得到乘法運(yùn)算值，乘法運(yùn)算的搭建結(jié)構(gòu)可以見圖3。圖3設(shè)計(jì)的時(shí)候使用P0,P1,P2,P3四個(gè)四位向量來(lái)代表兩個(gè)4位二進(jìn)制數(shù)每位相乘的結(jié)果，并按照順序分別使用12個(gè)加法器完成對(duì)這16個(gè)數(shù)字的運(yùn)算，得到乘法結(jié)果。值得注意的是在搭建這個(gè)乘法器時(shí)，應(yīng)該對(duì)布線特別小心。因?yàn)榻Y(jié)果相對(duì)比較復(fù)雜，因而在使用Modelsim編輯程序的時(shí)候，最好將各個(gè)數(shù)字按照條件分別編號(hào)，最后在分配各個(gè)加法器輸入的時(shí)候就不會(huì)出錯(cuò)，而且速度相對(duì)起不按規(guī)矩編號(hào)的要

6、快得多！最終輸出將以8位向量來(lái)表示這個(gè)乘法結(jié)果。2.移位器：本設(shè)計(jì)的ALU中的移位器的作用是將一個(gè)4位二進(jìn)制數(shù)，擴(kuò)展為8位后，對(duì)其進(jìn)行移位操作。而移位則分為左移位和右移位，控制移位數(shù)則是第二個(gè)輸入的4位二進(jìn)制數(shù)。因此設(shè)計(jì)分為兩個(gè)部分，左移位器和右移位器！本設(shè)計(jì)中，兩個(gè)輸入均為4位二進(jìn)制數(shù)，且第二個(gè)二進(jìn)制數(shù)設(shè)定為有符號(hào)數(shù)，如果為負(fù)則網(wǎng)反向移位。因此數(shù)位控制則由第二個(gè)輸入的后三位控制。3.選擇器：選擇器的主要作用是由一個(gè)三位二進(jìn)制來(lái)控制ALU的輸出，我們將對(duì)應(yīng)關(guān)系總結(jié)為表1。從表中便可以很清楚地看出輸入與輸出的對(duì)應(yīng)關(guān)系。InstructionsFunctions001Adder010Subtrac

7、tor011Multiplier100Left Shift101Right ShiftothersReversed表1.輸入與輸出控制關(guān)系表實(shí)際設(shè)計(jì)結(jié)構(gòu)如圖4：圖4三 系統(tǒng)程序與仿真3.1 模塊程序設(shè)計(jì)本設(shè)計(jì)的模塊設(shè)計(jì)主要分為6個(gè)模塊：（1) 帶符號(hào)運(yùn)算加法器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity final_adder is port( data_a,data_b: in std_logic_vector(3 dow

8、nto 0); data_s: out std_logic_vector(7 downto 0);end final_adder;architecture behav of final_adder iscomponent full_adder is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; cout: out std_logic; s : out std_logic);end component;signal cout1,cout2,cout3,cout4:std_logic;signal a,b,data_s

9、1:std_logic_vector(4 downto 0); begin a<= data_a(3) & data_a; b<= data_b(3) & data_b; u0:full_adder port map(a=>a(0),b=>b(0),cin=>'0',s=>data_s1(0),cout=>cout1); u1:full_adder port map(a=>a(1),b=>b(1),cin=>cout1,s=>data_s1(1),cout=>cout2); u2:full_

10、adder port map(a=>a(2),b=>b(2),cin=>cout2,s=>data_s1(2),cout=>cout3); u3:full_adder port map(a=>a(3),b=>b(3),cin=>cout3,s=>data_s1(3),cout=>cout4); u4:full_adder port map(a=>a(4),b=>b(4),cin=>cout4,s=>data_s1(4); data_s<="111"&data_s1 when d

11、ata_s1(4)='1' else "000"&data_s1 ; end behav; 說(shuō)明：加法器采用的是普通的四位加法器，采用全加器的串行連接完成，同時(shí)由于輸出位數(shù)的要求我們使用了強(qiáng)制補(bǔ)位的方法將輸出的四位加法結(jié)果補(bǔ)至八位的標(biāo)準(zhǔn)輸出位數(shù)。 其中，全加器的構(gòu)建為：library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;entity full_adder is Port ( a : in std

12、_logic; b : in std_logic; cin : in std_logic; cout: out std_logic; s : out std_logic);end full_adder;architecture Behavioral of full_adder isbegin s <= a xor b xor cin; cout <= (a and b) or (a or b) and cin);end Behavioral;（2) 帶符號(hào)運(yùn)算減法器library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG

13、IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;entity final_sub is port( data_a,data_b: in std_logic_vector(3 downto 0); data_s: out std_logic_vector(7 downto 0);end final_sub;architecture behav of final_sub iscomponent adder for_sub is port( data_a,data_b: in std_logic_vector(3 downto 0); data_s: ou

14、t std_logic_vector(7 downto 0);end component;signal b1,b2:std_logic_vector(3 downto 0);begin b1<=not(data_b); b2<=b1+"0001" u0: adderfor_sub port map(data_a=>data_a,data_b=>b2,data_s=>data_s);end behav; 說(shuō)明：減法器是采用將第二個(gè)數(shù)據(jù)取補(bǔ)碼，然后使用加法器進(jìn)行數(shù)據(jù)一和數(shù)據(jù)二補(bǔ)碼數(shù)據(jù)的加法，以此來(lái)完成減法功能，同時(shí)由于補(bǔ)碼的問(wèn)題，減法器需要額外的對(duì)

15、其進(jìn)行8的修正，以此來(lái)完善減法器。其中，相應(yīng)的加法器為：library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;entity adderfor_sub is port( data_a,data_b: in std_logic_vector(3 downto 0); data_s: out std_logic_vector(7 downto 0);end adderfor_sub;architecture behav of adderfor_s

16、ub iscomponent full_adder is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; cout: out std_logic; s : out std_logic);end component;signal cout1,cout2,cout3,cout4:std_logic;signal a,b,data_s1:std_logic_vector(4 downto 0); begin a<= data_a(3) & data_a; process(data_b) begin if (d

17、ata_b="1000") then b<='0'&data_b ; else b<= data_b(3) & data_b; end if ;end process; u0:full_adder port map(a=>a(0),b=>b(0),cin=>'0',s=>data_s1(0),cout=>cout1); u1:full_adder port map(a=>a(1),b=>b(1),cin=>cout1,s=>data_s1(1),cout=>

18、;cout2); u2:full_adder port map(a=>a(2),b=>b(2),cin=>cout2,s=>data_s1(2),cout=>cout3); u3:full_adder port map(a=>a(3),b=>b(3),cin=>cout3,s=>data_s1(3),cout=>cout4); u4:full_adder port map(a=>a(4),b=>b(4),cin=>cout4,s=>data_s1(4); data_s<="111"&a

19、mp;data_s1 when data_s1(4)='1' else "000"&data_s1 when data_s1(4)='0' ;end behav; （3) 無(wú)符號(hào)運(yùn)算乘法器library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;entity multiplier is port( data_a,data_b: in std_logic_vector(3 downto

20、0); data_P: out std_logic_vector(7 downto 0);end multiplier;architecture behav of multiplier iscomponent full_adder Port ( a : in std_logic; b : in std_logic; cin : in std_logic; cout: out std_logic; s : out std_logic);end component;subtype ABC is std_logic_vector(0 to 3);type type_pp is array (0 to

21、 3) of ABC; signal pp: type_pp; signal i,j:integer; signal s0,s1,c1,s2,c2,s3,s4,c4,s5,c5,s6,s7,c7,s8,c8,s9,s10:std_logic; beginprocess(data_a,data_b) begin N1:for i in 0 to 3 loop N2:for j in 0 to 3 loop next N1 when j>3; pp(i)(j)<=data_a(i) and data_b(j);end loop N2;end loop N1;end process; d

22、ata_p(0) <=pp(0)(0); u0:full_adder port map(a=>pp(1)(0),b=>pp(0)(1),cin=>'0',cout=>s0,s=>data_p(1); u1:full_adder port map(a=>pp(1)(1),b=>pp(0)(2),cin=>'0',cout=>s1,s=>c1); u2:full_adder port map(a=>pp(1)(2),b=>pp(0)(3),cin=>'0',cout=

23、>s2,s=>c2); u3:full_adder port map(a=>pp(2)(0),b=>c1,cin=>s0,cout=>s3,s=>data_p(2); u4:full_adder port map(a=>pp(2)(1),b=>c2,cin=>s1,cout=>s4,s=>c4); u5:full_adder port map(a=>pp(1)(3),b=>pp(2)(2),cin=>s2,cout=>s5,s=>c5); u6:full_adder port map(a=&g

24、t;pp(3)(0),b=>c4,cin=>s3,cout=>s6,s=>data_p(3); u7:full_adder port map(a=>pp(3)(1),b=>c5,cin=>s4,cout=>s7,s=>c7); u8:full_adder port map(a=>pp(2)(3),b=>pp(3)(2),cin=>s5,cout=>s8,s=>c8); u9:full_adder port map(a=>c7,b=>s6,cout=>s9,cin=>'0'

25、,s=>data_p(4); u10:full_adder port map(a=>c8,b=>s7,cin=>s9,cout=>s10,s=>data_p(5); u11:full_adder port map(a=>pp(3)(3),b=>s8,cin=>s10,cout=>data_p(7),s=>data_p(6);end behav;說(shuō)明：乘法器主要是采用了二維數(shù)組以及循環(huán)語(yǔ)句的方式對(duì)兩個(gè)數(shù)據(jù)的權(quán)位進(jìn)行了采樣一次，一次來(lái)完成后面的通過(guò)加法器串行連接的8位乘法器的運(yùn)算。（4) 左移位器library ieee;use i

26、eee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity LS is port(a:in std_logic_vector(3 downto 0); b:out std_logic_vector(7 downto 0); ctr:in std_logic_vector(3 downto 0);end LS; architecture behav of LS is signal b1:std_logic_vector(7 downto 0):=(others=>

27、9;0');begin process(a,ctr) begin b1 <="00000000" case ctr(2 downto 0) is when "000" => b1(3 downto 0) <= a(3 downto 0) ; when "001" => b1(4 downto 1) <= a(3 downto 0) ; when "010" => b1(5 downto 2) <= a(3 downto 0) ; when "011&quo

28、t; => b1(6 downto 3) <= a(3 downto 0) ; when "100" => b1(7 downto 4) <= a(3 downto 0) ; when "101" => b1(7 downto 5) <= a(2 downto 0) ; b1(0) <= a(3) ; when "110" => b1(7 downto 6) <= a(1 downto 0) ; b1(1 downto 0) <= a(3 downto 2) ; when &

29、quot;111" => b1(7) <= a(0) ; b1(2 downto 0) <= a(3 downto 1); when others=>null; end case; end process;b<=b1;end behav;（5) 右移位器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity RS is port(a:in std_logic_vector(3 downto 0)

30、; b:out std_logic_vector(7 downto 0); ctr:in std_logic_vector(3 downto 0);end RS; architecture behav of RS is signal b1:std_logic_vector(7 downto 0):=(others=>'0');begin process(a,ctr) begin b1 <="00000000" case ctr(2 downto 0) is when "000" => b1(3 downto 0) <

31、;= a(3 downto 0) ; when "111" => b1(4 downto 1) <= a(3 downto 0) ; when "110" => b1(5 downto 2) <= a(3 downto 0) ; when "101" => b1(6 downto 3) <= a(3 downto 0) ; when "100" => b1(7 downto 4) <= a(3 downto 0) ; when "011" =>

32、; b1(7 downto 5) <= a(2 downto 0) ; b1(0) <= a(3) ; when "010" => b1(7 downto 6) <= a(1 downto 0) ; b1(1 downto 0) <= a(3 downto 2) ; when "001" => b1(7) <= a(0) ; b1(2 downto 0) <= a(3 downto 1); when others=>null; end case; end process;b<=b1;end be

33、hav;說(shuō)明：左移右移的原理是想通的，他們都是采用了逐個(gè)分析數(shù)據(jù)的方式對(duì)數(shù)據(jù)采取人為的判斷操作，采樣0-2這3個(gè)位數(shù)的數(shù)據(jù)以此來(lái)分析移位的方法。3.2 頂層結(jié)構(gòu)程序設(shè)計(jì)頂層設(shè)計(jì)主要實(shí)現(xiàn)的功能為調(diào)用各個(gè)模塊實(shí)現(xiàn)綜合，并且能夠在ISE上成功仿真，并且通過(guò)chipscope下載程序到FPGA板上。主要就是排線部位的設(shè)計(jì)和編程，這就需要將以上所有模塊布線實(shí)現(xiàn)一個(gè)整體ALU的模塊。相應(yīng)的代碼為：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;enti

34、ty ALU is port( rst : in std_logic; clk : in std_logic; ensure : in std_logic; datin1 : in std_logic_vector( 3 downto 0 ); datin2 : in std_logic_vector( 3 downto 0 ); inst : in std_logic_vector( 2 downto 0); datout : out std_logic_vector( 7 downto 0) );end ALU;architecture behav of ALU iscomponent f

35、inal_adder is port( data_a,data_b: in std_logic_vector(3 downto 0); data_s: out std_logic_vector(7 downto 0) );end component;component final_sub is port( data_a,data_b: in std_logic_vector(3 downto 0); data_s: out std_logic_vector(7 downto 0);end component;component RS is port(a:in std_logic_vector(

36、3 downto 0); b:out std_logic_vector(7 downto 0); ctr:in std_logic_vector(3 downto 0) );end component;component LS is port(a:in std_logic_vector(3 downto 0); b:out std_logic_vector(7 downto 0); ctr:in std_logic_vector(3 downto 0) );end component;component multiplier is port(data_a,data_b:in std_logic

37、_vector(3 downto 0); data_p:out std_logic_vector(7 downto 0) );end component;signal datoutadd,datoutsub,datoutrs,datoutls,datoutmul:std_logic_vector(7 downto 0);signal datout_temp:std_logic_vector(7 downto 0);signal datin1_temp,datin2_temp :std_logic_vector( 3 downto 0 ); begin process(clk,rst)begin

38、 if(rst = '1')then datin1_temp <= (others => '0'); datin2_temp <= (others => '0'); elsif(clk'event and clk = '1')then datin1_temp <= datin1; datin2_temp <= datin2; end if;end process; u0:final_adder port map(data_a=>datin1_temp,data_b=>datin2_temp,data_s=>datoutadd); u1:final_sub port map(data_a=>datin1_temp,data_b=>datin2_temp,data_s=>datoutsub); u2:RS port map(a=>datin1_temp,b=>datoutrs,ctr=>datin2_t