DRAM內存顆粒測試簡介PPT課件(PPT 37頁)

1、Introduction to DRAM Testing- DRAM inside team- 2015.May第1頁，共37頁。AgendaBasis of TestingTypical DRAM Testing FlowBurn-inDC Test (Open/Short, Leakage, IDD)Functional Test & Test PatternSpeed Test第2頁，共37頁。DRAM ManufactureWaferAssemblyFinal TestingFinal Product第3頁，共37頁。Why Testing?To screen out defectWa

2、fer defectAssembly defectMake sure product meet spec of customerVoltage guard bandTemperature guard bandTiming guard bandComplex test patternCollect data for design & process improvementQualityReliabilityCostEfficiency第4頁，共37頁。IC Test MethodologyIC TesterPPSDriverComparatorDUT* DUT = Device Under Te

3、stPower SupplyOutputInputTesting of a DUT: 1. To connect PPS, Driver, Comparator & GND. 2. To apply power to DUT. 3. To input data to DUT (Address, Control Command, Data) 4. To compare output with “expect value” and judge PASS/FAIL第5頁，共37頁。Basic Test SignalDigital Waveform ElementsLogicVoltageTiming

4、第6頁，共37頁。Typical DRAM Final Test FlowBurn-inMBT (Monitor Burn in Test): Stress to screen out Early FailuresTBT (Test Burn in Test): Long time pattern testVery Low Speed(5-20MHz), High Parallel Test (10-20Kpcs/oven), Low CostCore TestDC TestFunctional TestLow Speed (DDR3 667MHz), Typical tester Advan

5、test T5588 + 512DUT HiFixSpeed TestSpeed & AC Timing TestFull Speed (DDR3 1600MHz and above), Advantest T5503 + 256DUT HiFixBackendMarking Ball Scan Visual Inspection Baking Vacuum Pack 第7頁，共37頁。DRAM Burn-in (MBT)MBT is to stress IC and screen out early failuresHigh Temperature Stress (125degC)High

6、Voltage StressStressful Pattern BIOperation TimeFailure RateInfant MortalityNormal LifeWorn outNew productMature productBath Curve第8頁，共37頁。DRAM Burn-in (TBT)TBT is for long time test patternsMultiple temperature tested (e.g. 88C, 25C, -10C)Long test time at low speedPatterns cover all cell arraysNo

7、Stressful conditionHigh parallel test count, low costBoth MBT and TBT does NOT test DC (Ando Oven)第9頁，共37頁。DRAM Advantest TestDC TestOpen/Short testLeakage testIDD testFunctional Test (Core Test)Different parameter & Pattern for each functionTo check DRAM can operate functionallySpeed TestTiming tes

8、t different speed grade第10頁，共37頁。DC Test DC Test Method:ISVM:I SourceV MeasureVSIMV SourceI MeasureVCCVCC第11頁，共37頁。DC Test Open ShortPurpose: Check connection between pins and test fixture Check if pin to pin is short in IC package Check if pin to wafer pad has open in IC package Check if protection

9、 diodes work on die It is a quick electrical check to determine if it is safe to apply power Also called Continuity Test第12頁，共37頁。DC Test Open ShortFailure Mode:a) Wafer ProblemDefect of diodeb) Assembly ProblemWire bondingSolder ballc) Contact ProblemSocket issueCore CircuitDefective diodeSocket Po

10、go Pin defectWire touched第13頁，共37頁。DC Test Open ShortO/S Test Condition:ProcedureGround all pins ( including VDD)Using PMU force 100 uA, one pin at a timeMeasure voltageFail open test if the voltage is greater than 1.5 VFail short test if the voltage is less than 0.2 V100uA0.65 VPMUforcesenseforceMe

11、asureVss=0Vdd=0100uAFail OpenPassFail Short 1.5V 0.2 V1.5 V-100uA-0.65 VPMUforcesenseforceMeasureVss=0Vdd=0-100uAISVMOther=0Typical -0.65V第15頁，共37頁。DC Test LeakagePurpose: Verify resistance of pin to VDD/VSS is high enough Verify resistance of pin to pins is high enough Identify process problem in C

12、MOS device 第16頁，共37頁。DC Test LeakageILIH/ILIL: Input Leakage High/Low To verify input buffers offer a high resistance No preconditioning pattern appliedILOH/ILOL: Output Leakage High/Low To verify tri-state output buffers offer a high resistance in off state Test requires preconditioning pattern Per

13、formed only on three-state outputs and bi-directional pins第17頁，共37頁。DC Test LeakageFailure Mode:a) Wafer problemb) Assembly problemc) Socket Contact problem (short)Die crackBall touch (Short)第18頁，共37頁。DC Test Input Leakage LowTest Condition:ProcedureApply VDDmax (2.0V)Pre-condition all input pins to

14、 logic 1 (high voltage)Using PMU (Parametric Measure Unit) force Ground to tested pinWait for 1 to 5 msecMeasure current of tested pinFail IIL test if the current is less than 1.5 uAPassFail 1.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILIHVLSICore“1”“0” all input pins = 0VONOFF第20頁，共37頁。DC Test Output

15、Leakage LowTest Condition:ProcedureApply VDDmax (2.0V)Pre-condition the DUT to tristate with specific patternWait a specific timeUsing PMU force VDDMAX to tested I/O pinMeasure currentFail IOH test if the current is greater than +4.5uA or less than -4.5uAPassFailGT 4.5 uA0.0 V-10nAPMUforceMeasureVss

16、=0VDDmaxILOLVLSICoreOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“0”All input pins = 2.3VAll output pins=0V/2.3V第21頁，共37頁。DC Test Output Leakage HighTest Condition:ProcedureApply VDDmax (2.0V)Pre-condition the DUT to tristate with specific patternWait a specific timeUsing PMU force VDDMAX to tested

17、I/O pinMeasure currentFail IOH test if the current is greater than +4.5uA or less than -4.5uAPassFailGT 4.5 uA2.0 V10nAPMUforceMeasureVss=0VDDmaxILOHVLSICoreAll input pins = 2.3VAll output pins=0V/2.3VOFFOFFPre-condition Pattern 1/0FailLT -4.5 uA“1”第22頁，共37頁。DC Test Test Program Condition第23頁，共37頁。D

18、C Test IDDPurpose:IDD (or ICC) measures current of Vdd pin in different statesIt makes sure power consumption not higher than expected.Failure Mode:Wafer process issueAssembly issueContact issue (VDD, VSS)第24頁，共37頁。DC Test Static IDDTest Condition:ProcedureUsing PMU to apply VDDmax on VDD pinExecute

19、 Pre-condition patternStop the patternWait a specific time Measure current flowing into VDD pins while device is in idleFail IDD test if the current is greater than IDD spec. ( Normal in mA)PassFailGT spec2.0 V10mAPMUforcesenseforceMeasureVDDIDDVLSIVSS=0Pre-condition Pattern第25頁，共37頁。DC Test Dynamic

20、 IDDTest Condition:ProcedureUsing PMU to apply VDDmax on VDD pinExecute Pre-condition patternWait a specific time Measure current flowing into VDD pins while device is executing patternFail IDD test if the current is greater than IDD spec. ( Normal in mA)Stop patternPassFailGT spec2.0 V80mAPMUforces

21、enseforceMeasureVDDIDDVLSIVSS=0Pre-condition PatternPre-condition Pattern第26頁，共37頁。Function TestTo verify DRAM can operate functionally, we need to do Functional test.- Easy Function Test (EFT)It check basic IC functionality by reading “0” (or “1”) from all cell after writing “0” (or “1”) in. Typica

22、l Test Pattern: March Pattern (e.g. March C-)March C- Algorithm: (w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0); (r0)Operation Count: 10*nScan type: X-Scan (X inc - Y inc), Y-Scan(Y inc - X inc)Fault Coverage: Most of Failure Mode第27頁，共37頁。0000000000000000000000000000000R0000000000000000W100000000000000R01000

23、00000000000W110000000000000R0110000000000000W111000000000000R0111000000000000W1111000000001111111100001111111111111111111111111111DRAM Test Pattern (X-scan)YX000110110001101128.第28頁，共37頁。DRAM Test March Pattern29.第29頁，共37頁。DRAM Test Failure ModeStuck-at Fault (SAF)Coupling Fault (CF)Shorts between d

24、ata linesCrosstalk between data linesTransistion Fault (TF)Cell can be set to 0 and not to 1 (or vice versa) when its operatedAddressing Fault (AF)Address line stuckOpen in address lineShorts between address linesWrong accessCell stuckDriver stuckData line stuckNeighbor Pattern Sensitive Fault (NPSF

25、)Pattern sensitive interaction between cellsData Retention Fault (DRF)Data can not kept same status in cell as time pass第30頁，共37頁。DRAM Test March PatternMarch C- is the most effective31.第31頁，共37頁。DRAM Test 1HTDefect ModeOPENLEAKIDDEFTTESTER RELATEDWAFER ISSUEDIE CRACKDIE CHIPSURFACE DAMAGENG DieNON DIENON WIREAE OPENWIRE SHORT WITH WIREWIRE SHORT WITH DIE EDGEWIRE SWEEPNON BROKEN INNER LEADOTHERS: S