非同步式計(jì)數(shù)器的運(yùn)作ppt課件

1、Chapter 9 Counters計(jì)數(shù)器Asynchronous Counter Operation 非同步式計(jì)數(shù)器的運(yùn)作Synchronous Counter Operation 同步式計(jì)數(shù)器的運(yùn)作Up/Down Synchronous Counters 上 / 下數(shù)的同步式計(jì)數(shù)器Design of Synchronous Counters 同步式計(jì)數(shù)器的設(shè)計(jì)Cascaded Counters 串接計(jì)數(shù)器Counter Decoding 計(jì)數(shù)器的解碼Counter Applications 計(jì)數(shù)器的應(yīng)用Troubleshooting 檢修Logical Symbols with Depen

2、dency Notation 具有相依註標(biāo)的邏輯符號(hào)Programmable Logic 可程式邏輯Digital System Application 數(shù)位系統(tǒng)的應(yīng)用1Figure 8-40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All right

3、s reserved.Flip-Flop Applications 正反器的用途除法器JKClkQQ00Q0Q0不變0101Reset1010Set11Q0Q0轉(zhuǎn)態(tài)2Figure 9-1 A 2-bit asynchronous binary counter. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作Figure 9-2 Timing di

4、agram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.100111003Figure 9-3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Je

5、rsey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作4Figure 9-4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作5Figure 9-5 Four-bit

6、asynchronous binary counter and its timing diagram. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作例題9-1 如圖9-5所示為一個(gè)4位元的非同步二進(jìn)制計(jì)數(shù)器, 每一個(gè)正反器都是負(fù)緣觸發(fā)而且有一個(gè)10ns的極際延遲時(shí)間. (1)設(shè)計(jì)各正反器輸出的時(shí)序圖, (2)算出從Clock輸入加訊號(hào)進(jìn)去到Q3

7、輸出的延遲時(shí)間, (3)算出最高任務(wù)頻率.Sol:(2) tp(Total) = 4 x 10ns = 40ns(3) fmax = 1/ tp(Total) = 1/40ns = 25MHz6Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作Figure 9-6 An asynchronously clocked decade counter wi

8、th asynchronous recycling.7Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.例題9-2 證明一個(gè)非同步的計(jì)數(shù)器如何除12, 從二進(jìn)制的0000算到1011.1. 非同步式計(jì)數(shù)器的運(yùn)作Figure 9-7 Asynchronously clocked modulus-12 counter with asynchronous recycling.很尖銳

9、的脈波8FigureA-21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1

10、. 非同步式計(jì)數(shù)器的運(yùn)作9Figure A-22 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作1

11、0Figure A-23 74LS93A connected as a modulus-12 counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.1. 非同步式計(jì)數(shù)器的運(yùn)作例題9-3 證明74LS93A 如何作為一個(gè)除12的計(jì)數(shù)器.11A 2-bit synchronous binary counter.Thomas L. FloydDigital Fundam

12、entals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作Figure 9-10 Timing diagram for the counter of Figure 9-11.12Figure 9-9 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assu

13、med to be equal).Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作第一個(gè)脈波第二個(gè)脈波第三個(gè)脈波第四個(gè)脈波解釋前一頁(yè)每次Clock來(lái)時(shí)Q0及Q1的變化13Figure 9-11 A 3-bit synchronous binary counter. Thomas L. FloydDigital Fundamentals, 8eCopy

14、right 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作Figure 9-12 Timing diagram for the counter of Figure 9-14.14Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved

15、.2. 同步式計(jì)數(shù)器的運(yùn)作FF2在Q0Q1同時(shí)為1時(shí),下一個(gè)脈波來(lái)會(huì)改變狀態(tài), FF3則在Q0Q1Q2同時(shí)為1時(shí),下一個(gè)脈波來(lái)才會(huì)改變狀態(tài), Figure 9-13 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.15Figure 9-14 A synchronous BCD decade counter.Thomas L. FloydDigital Fundamentals, 8

16、eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作Figure 9-15 Timing diagram for the BCD decade counter (Q0 is the LSB).16Figure A-24 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with si

17、xteen states.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作17Figure A-25 Timing example for a 74HC163.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle Ri

18、ver, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作18Figure A-26 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All

19、 rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作19Figure A-27 Timing example for a 74LS160.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.2. 同步式計(jì)數(shù)器的運(yùn)作20Figure 9-16 A basic 3-bit up/down synchronous counter. Thomas L. FloydDigital

20、Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.3. 上 / 下數(shù)的同步式計(jì)數(shù)器21Figure 9-17 Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.3. 上 / 下數(shù)的同步式計(jì)數(shù)器22Fig

21、ure A-28 The 74HC190 up/down synchronous decade counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.3. 上 / 下數(shù)的同步式計(jì)數(shù)器23Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Sadd

22、le River, New Jersey 07458All rights reserved.3. 上 / 下數(shù)的同步式計(jì)數(shù)器Figure A-29 Timing example for a 74HC190.24Figure 9-18 General clocked sequential circuit.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)

23、激勵(lì)線狀態(tài)變數(shù)線輸入線與狀態(tài)變數(shù)線加到組合邏輯電路產(chǎn)生激勵(lì)訊號(hào)線Previous State Present State Next State25Figure 9-19 State diagram for a 3-bit Gray code counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)步驟一: 畫出狀態(tài)圖26Figure 9-20

24、 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)步驟二: 寫出 下一狀態(tài)表.步驟三: 寫出 正反器的暫態(tài)表.步驟四: 根據(jù)下一狀態(tài)表及正反器的暫態(tài)表填寫卡

25、諾圖.27Figure 9-21 Karnaugh maps for present-state J and K inputs.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)28步驟五: 寫出各正反器的輸入端之邏輯表示式J0 = Q2Q1 + Q2Q1 = Q2 xor Q1K0 = Q2Q1 + Q2Q1 = Q2 xor Q1J1 = Q2Q0

26、K1 = Q2Q0J2 = Q1Q0K2 = Q1Q0Figure 9-22 Three-bit Gray code counter. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)步驟六: 畫出電路圖29Figure 9-23Output TransitionsQN QN+1Flip-Flop Inputs J K 0 0 0 x 0 1 1 x

27、 1 0 x 1 1 1 x 0Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)例題9-5 運(yùn)用JK正反器, 設(shè)計(jì)一個(gè)如圖9-32所示不按照二進(jìn)制計(jì)數(shù)順序的計(jì)數(shù)器.Present StateQ2 Q1 Q0Next StateQ2 Q1 Q0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 130Figur

28、e 9-24Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)31Figure 9-25Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserv

29、ed.J0 = 1, K = Q2J1 = K1 = 1J2 = K2 = Q14. 同步式計(jì)數(shù)器的設(shè)計(jì)32Figure 9-26 State diagram for a 3-bit up/down Gray code counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.例題9-6 試設(shè)計(jì)一個(gè)3位元的格雷碼同步式上下數(shù)計(jì)數(shù)器, 當(dāng)UP/DOWN為1時(shí)往上數(shù), 為

30、0時(shí)往下數(shù).4. 同步式計(jì)數(shù)器的設(shè)計(jì)33Present StateNext StateY=0(Down) Y=1(Up)Q2 Q1 Q0Q2 Q1 Q0Q2 Q1 Q0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0Output TransitionsQN QN+1Flip-Flop Inputs J K 0 0 0 x 0 1 1 x 1 0 x 1 1

31、1 x 04. 同步式計(jì)數(shù)器的設(shè)計(jì)34Figure 9-27 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.4. 同步式計(jì)數(shù)器的設(shè)計(jì)35Figure 9-28 Three-bit up/dow

32、n Gray code counter.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.步驟五: 寫出各正反器的輸入端之邏輯表示式步驟六: 畫出電路圖4. 同步式計(jì)數(shù)器的設(shè)計(jì)36Figure 9-29 Two cascaded counters (all J and K inputs are HIGH).Thomas L. FloydDigital Fundamentals

33、, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.5. 串接計(jì)數(shù)器Figure 9-30 Timing diagram for the cascaded counter configuration of Figure 9-38.37Figure 9-31 A modulus-100 counter using two cascaded decade counters.Thomas L. FloydDigital Fundamentals, 8e

34、Copyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.5. 串接計(jì)數(shù)器Figure 9-32 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.38Figure 9-33Thomas L. FloydDigital Fundamentals, 8

35、eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.例題9-7 試算出圖9-42中兩個(gè)電路全部各除多少? Sol:9-42(a)8 x 12 x 16 = 15369-42(b) 10 x 4 x 7 x 5 = 14005. 串接計(jì)數(shù)器39Figure 9-34 A divide-by-100 counter using two 74LS160 decade counters.Thomas L. FloydDigital Fundamentals,

36、8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.5. 串接計(jì)數(shù)器例題9-8 運(yùn)用74LS160 計(jì)數(shù)器設(shè)計(jì)一個(gè)電路, 將1MHz的訊號(hào)從Clock端輸入, 輸出端得到10KHz.40Figure 9-35 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in bin

37、ary order (the right-most bit D0 is the LSB in each counter).Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.5. 串接計(jì)數(shù)器從63C0算到FFFF, 即除以40,000.63C0H = 25,536.40,000 = 65535 25536 + 141解題步驟 (n,m,x,y 皆為正整數(shù))決定所需位元數(shù) n x

38、:所需除數(shù)決定所需74161個(gè)數(shù) m換算計(jì)數(shù)器初始值 y 換算成16進(jìn)位值畫電路圖42計(jì)數(shù)器之解碼對(duì)計(jì)數(shù)器序列中任何指定狀態(tài)實(shí)作其解碼邏輯 運(yùn)用閃控法Strobe消除解碼時(shí)的脈衝干擾計(jì)數(shù)器解碼器Output=1At counter = 66. 計(jì)數(shù)器的解碼43Figure 9-36 Decoding of state 6 (110). Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights rese

39、rved.6. 計(jì)數(shù)器的解碼44Figure 9-37 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.6. 計(jì)數(shù)器的解碼45Figure 9-38 A basic decade (BCD) counter and decoder.Thomas

40、 L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.6. 計(jì)數(shù)器的解碼46Figure 9-39 Outputs with glitches from the decoder in Figure 9-38. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.6

41、. 計(jì)數(shù)器的解碼Decoding Glitches47Figure 9-40 The basic decade counter and decoder with strobing to eliminate glitches.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.6. 計(jì)數(shù)器的解碼48Figure 9-41 Strobed decoder outputs for t

42、he circuit of Figure 9-49.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.6. 計(jì)數(shù)器的解碼49Figure 9-42 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-5

43、2 and 9-53.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.7. 計(jì)數(shù)器的應(yīng)用50Figure 9-43 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary orde

44、r (the right-most bit is the LSB).Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.7. 計(jì)數(shù)器的應(yīng)用51Figure 9-44 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most b

45、it is the LSB.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.7. 計(jì)數(shù)器的應(yīng)用52Figure 9-45 Functional block diagram for parking garage control.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education,

46、 Inc.Upper Saddle River, New Jersey 07458All rights reserved.7. 計(jì)數(shù)器的應(yīng)用車輛停車控制: 最多可停100輛, 當(dāng)停滿100輛時(shí)指示燈亮起, 同時(shí)柵欄放下, 當(dāng)不滿100輛時(shí)指示燈滅掉, 同時(shí)柵欄收起.53Figure 9-46 Logic diagram for modulus-100 up/down counter for automobile parking control.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.7. 計(jì)數(shù)器的應(yīng)用車輛停車控制54Figure 9-47 Parallel-to-serial data conversion logic.Thomas L. FloydDigital Fundamentals, 8eCopyright 2003 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserv