文本07通信初稿

1、 前第一章 FPGA簡 前第一章 FPGA簡FPGA概FPGA基本結(jié)FPGA的工作原FPGA的設(shè)計(jì)流設(shè)計(jì)輸設(shè)計(jì)仿實(shí)數(shù)字時鐘設(shè)計(jì)及MAX+PLUSEII的介2.1數(shù)字時鐘的原2.2. 2.3數(shù)字鐘的功能要2.4MAXPLUS簡程序設(shè)計(jì)與實(shí)驗(yàn)仿主程序代碼設(shè)計(jì)與仿真結(jié)主程序源代實(shí)驗(yàn)仿真結(jié)24進(jìn)制代碼設(shè)計(jì)與仿真結(jié)24進(jìn)制源代實(shí)驗(yàn)仿真結(jié)60進(jìn)制代碼設(shè)計(jì)與仿真結(jié)60進(jìn)制源代實(shí)驗(yàn)仿真結(jié)去抖代碼設(shè)計(jì)與仿真結(jié)去抖源代去抖代碼設(shè)計(jì)與仿真結(jié)去抖源代3.4.2 實(shí)驗(yàn)仿真結(jié)果. 總結(jié)與體參考文附錄致FPGA本文是人研究成果的基礎(chǔ)上，面向?qū)嶋H應(yīng)用的需求在 Quartus 開發(fā)環(huán)境下,VerilogHDL硬件描述語言設(shè)計(jì)了

2、一個可以在上實(shí)現(xiàn)的數(shù)字時鐘.到FPGAAlteraDE2開發(fā)板上進(jìn)行了功能驗(yàn)證. VHDL隨著現(xiàn)工藝的改進(jìn)，F(xiàn)PGA的等效系統(tǒng)門達(dá)到到幾百萬門，而且工作頻率也隨FPGA本文是人研究成果的基礎(chǔ)上，面向?qū)嶋H應(yīng)用的需求在 Quartus 開發(fā)環(huán)境下,VerilogHDL硬件描述語言設(shè)計(jì)了一個可以在上實(shí)現(xiàn)的數(shù)字時鐘.到FPGAAlteraDE2開發(fā)板上進(jìn)行了功能驗(yàn)證. VHDL隨著現(xiàn)工藝的改進(jìn)，F(xiàn)PGA的等效系統(tǒng)門達(dá)到到幾百萬門，而且工作頻率也隨提高。FPGA，消費(fèi)類電子中都大面積的使用。FPGAFPGA價格不斷降低，促使FPGAASIC功能模塊集成到了FPGA的：數(shù)字時鐘；FPGA技術(shù)；VHDLBa

3、sed onFPGAdigitalclock This r is on the basis of sors achievements, the demand for practical in Quartus development environment, use Verilog HDL hardware description Based onFPGAdigitalclock This r is on the basis of sors achievements, the demand for practical in Quartus development environment, use

4、 Verilog HDL hardware description design a he FPGArealizing digital clock. Through FPGAdesign code downloaded the development platform Altera DE2 development board. Validate the function by language description hardware description digital clock function and the completion of function of odule,throu

5、ghysisand simulation waveform simulation tthisdesign digital clockfinish the expectedWith modern chip technology improvement, FPGAequivalent system door to door, and work to millions of frequency increases. The FPGAalso lots of appeared in electronic products. communications industry, electronic equ

6、ipment, safety network medical and various kinds er system, automotive electronics, electronics in the use of large area. The FPGA device high level egration, modification, short development cycle has ch as civil, the army used to themost from high-end tolow-end electronicdesign field Throughout fie

7、ld programmable logic on the development of history, its of attraction to market, depend on: the FPGA can not only make electronic miniaturization, er consumption, high reliability, and its software development cycle, less input, chip are lower, prompting the FPGA replaced the ASIC market; More and

8、more function egration, realize you to any digital circuit to realize, can customize various circuit; Reduce the fetter, bject to l chip really for their products tailored, in design s can be flexible change Keywords：Digitalclock,FPGAtechnology,VHDLlanguageFPGA1.1FPGA概的可編程邏輯器件，與之相應(yīng)的CPLD是復(fù)雜可編程邏輯器件（Co

9、mplex Programmable Logic Device）的簡稱，兩者的功能基本相同，只是實(shí)現(xiàn)原理略有不同，所以有時可以FPGA1.1FPGA概的可編程邏輯器件，與之相應(yīng)的CPLD是復(fù)雜可編程邏輯器件（Complex Programmable Logic Device）的簡稱，兩者的功能基本相同，只是實(shí)現(xiàn)原理略有不同，所以有時可以到了飛速的發(fā)展，同時也大大推動了1.2FPGA基本結(jié)FPGABlock Resource輸入信號是來自信號變換電路的輸出H1。這個函數(shù)發(fā)生器能實(shí)現(xiàn)3函數(shù)。這3個函數(shù)發(fā)生器結(jié)合起來，可實(shí)現(xiàn)多達(dá)9圖輸入信號是來自信號變換電路的輸出H1。這個函數(shù)發(fā)生器能實(shí)現(xiàn)3函數(shù)。這

10、3個函數(shù)發(fā)生器結(jié)合起來，可實(shí)現(xiàn)多達(dá)9圖由輸入觸發(fā)器、輸入緩沖器和輸出觸發(fā)/為為各種具有復(fù)雜功能的系統(tǒng)。IR，1.3 FPGA的工作原片識可以知道，對于一個n與非門電路的功能。FPGA1.4FPGA的設(shè)計(jì) entry（Simulation（Synthesize（Place&route（Synthesize（Place&route圖1.4.1設(shè)計(jì)輸入時是根據(jù)工程師的設(shè)計(jì)方法所設(shè)計(jì)的功能描述給計(jì)輸入方法有硬件描述語言HDL（ISEEditorSystemCoreGenerator、用于狀態(tài)機(jī)設(shè)計(jì)的 echnology高效的 echnology高效的1.4.2 等建立波形文件和測試向量（序列1.4.3

11、 實(shí)際的配置情況還有較大的差距。此時應(yīng)該使用FPGA，根據(jù)所的型號，將綜合輸出的邏輯網(wǎng)表適配到具體的FPGA器件上，具（Translate。MAXP+LUSEII2.1數(shù)字時鐘的原器和小時計(jì)數(shù)器。每個計(jì)數(shù)器又分別使用高地位2MAXP+LUSEII2.1數(shù)字時鐘的原器和小時計(jì)數(shù)器。每個計(jì)數(shù)器又分別使用高地位22進(jìn)制計(jì)數(shù)器，地位10進(jìn)制計(jì)數(shù)器數(shù)字時鐘首先是百分秒計(jì)數(shù)器按照系統(tǒng)時鐘CLK 50進(jìn)行計(jì)數(shù)，計(jì)數(shù)滿100后向從0圖2.2數(shù)字時須做到準(zhǔn)確穩(wěn)定。通常使用石英晶體振蕩電圖2.3 數(shù)字鐘的功能要時：當(dāng)人為時確時，可以分別對分圖2.3 數(shù)字鐘的功能要時：當(dāng)人為時確時，可以分別對分/時鐘進(jìn)行調(diào)整數(shù)據(jù)，

12、最大計(jì)時為999.9s提供時信號或中斷控制的時間基準(zhǔn)，具有廣泛的用途，基于PFGA的2.4 MAXPLUS開簡Altera的無關(guān)的可編程邏輯設(shè)計(jì)環(huán)境; 全集成化的一套可編程邏輯開發(fā)工具; 以直接放置74 。2.5MAXPLUSMAX+PLUS II 的編譯支持Altera 的FLEX 10K2.4 MAXPLUS開簡Altera的無關(guān)的可編程邏輯設(shè)計(jì)環(huán)境; 全集成化的一套可編程邏輯開發(fā)工具; 以直接放置74 。2.5MAXPLUSMAX+PLUS II 的編譯支持Altera 的FLEX 10K、FLEX 8K、MAX9000FLASHlogIC、MAX5000、Classic MAX+PLU

13、SII 的設(shè)計(jì)輸入、處理與校驗(yàn)功能一起提供了全集成化的一套可編程邏MAX+PLUSMAX+PLUS支持各種設(shè)計(jì)輸入，包括VHDL、Verilog 和Altera 的輸入綜合與校驗(yàn)工與CAE 工具接口符合EDIF200 和209、參數(shù)化模塊庫（LPM）、Verilog、VHDL 者可使用Altera 或標(biāo)準(zhǔn)CAE MAX+PLUS II 編譯器對Altera器件設(shè)計(jì)進(jìn)行編譯，并使用Altera 或其它CAE 校驗(yàn)工具進(jìn)行器件或板級仿真。 Data I/Oergraph、Minc、OrCAD 使用MAX+PLUS II 件2.6MAXPLUS設(shè)計(jì)向安用圖形輸入方式還是文本輸入方式，其設(shè)計(jì)流程是通用

14、的，如圖2.3圖圖主程序代碼設(shè)計(jì)與仿真結(jié)library ieee;useuse主程序代碼設(shè)計(jì)與仿真結(jié)library ieee;useuseuseentitynewclockport( endstd_logic_vector(7downto std_logic_vector(5 downto :instd_logic_vector(2downtoarchitectureaofnewclock component port( end : : : : : std_logic_vector(5downto0); component port( : : : std_logic_vector(5downt

15、o0); : :out end component;signal bin: signal dbs: signaldbm: signal dbh: signal enb: signal sec: signal bcd:signalstd_logic_vector(5: :out end component;signal bin: signal dbs: signaldbm: signal dbh: signal enb: signal sec: signal bcd:signalstd_logic_vector(5downtostd_logic_vector(5downto std_logic_

16、vector(5downtostd_logic_vector(5downto std_logic_vector(2downto0); std_logic_vector(7downto signal: signal s signalnum signal seg signal selsignal:std_logic_vector(2 downto: std_logic_vector(3downto:std_logic_vector(6 downto:std_logic_vector(5 downto le, :signal s:std_logic_vector(1downto0); signal

17、match: std_logic;signal glitter: signalu1: counter60 port map(clk,dbs,enb(0),clr,ecs,cys); u2:counter60portmap(clk,dbm,enb(1),clr,ecm,cym); u3: counter24 port map(clk,dbh,enb(2),clr,ech,cyh); clr= not key(0);sc=e(1) and eadj=secand (not sc) andecs= (sec and sc) or (adj and se(1) and not secm= (cys a

18、nd sc) or (adj and not se(1) and sech= (cym and sc) or (adj and not se(1) and not sselout= sel;gen:foradj=secand (not sc) andecs= (sec and sc) or (adj and se(1) and not secm= (cys and sc) or (adj and not se(1) and sech= (cym and sc) or (adj and not se(1) and not sselout= sel;gen:for iin 0to 6segout(

19、i)=seg(i)and(scor(glitterornotmatch); end generate;segout(7)=0; end block conj; signalq:std_logic_vector(25downto0); dly,sdly : std_logic;sifclkeventandclk=1then dly= q(22);sdly=q(16); q= q+1;end end glitter= sec=q(22)andnotdly; s= q(16 downto 14);sle= q(14) and notsel=000001whens=0000010whens=1else

20、 000100whens=2001000whens=3else 010000whens=4else 100000whens=5001000whens=3else 010000whens=4else 100000whens=5else enb=001when(s=0ors=1)else 010when(s=2ors=3)else 100when(s=4ors=5)else bin= dbs when enb=001else dbmwhenenb=010else dbh when enb=100else match=1when(s=0ors=1)ands 1when(s=2ors=3)ands 1

21、when(s=4ors=5)ands end block sel_bcd:block e=10) e=01)else e=00)num=bcd(3downto0)when(s=0ors=2ors=4)else bcd(7 downto 4);endblocksel_bcd; settime : blocksignalq:std_logic_vector(2downto0); signal set,ec : std_logic;sif elsifclkeventandclk=1then if ec=1thenendif; end if;end set=1whenelsifclkeventandc

22、lk=1then if ec=1thenendif; end if;end set=1whenq=7ec=nd e=q(1downto0); end block settime;key_d: signald0,d1,s,r,dly,ndly:std_logic; sifclkeventandclk=1then if sd1=d0;d0=key(2); s= d0 and d1;r=notd0andnotd1; end if;end end dly=rnorndly; ndly=s nor dly; dly_out= dly;end block wei:signald1,d0:std_logic

23、; wei:signald1,d0:std_logic; sif clk event and clk=1then d1=d0;d0=dly_out;end end diff=d0andnotd1; end block wei;bin_bcd:block bcd=00000000when bin = 0 else 00000001when bin = 1 else 00000010when bin = 2 else 00000011when bin = 3 else 00000100when bin = 4 else 00000101when bin = 5 else 00000110when

24、bin = 6 else 00000111when bin = 7 else 00001000when bin = 8 else 00001001when bin = 9 else 00010000whenbin=10else 00010001whenbin=11else 00010010whenbin=12else 00010011whenbin=13else 00010100when bin= 14 00010101when bin= 15 00010110whenbin00010110whenbin=16else 00010111whenbin=17else 00011000whenbi

25、n=18else 00011001whenbin=19else 00100000whenbin=20else 00100001whenbin=21else 00100010whenbin=22else 00100011whenbin=23else 00100100whenbin=24else 00100101whenbin=25else 00100110whenbin=26else 00100111whenbin=27else 00101000whenbin=28else 00101001whenbin=29else 00110000whenbin=30else 00110001whenbin

26、=31else 00110010whenbin=32else 00110011whenbin=33else 00110100whenbin=34else 00110101whenbin=35else 00110110whenbin=36else 00110111whenbin=37else 00111000whenbin=38else 00111001whenbin=39else 01000000whenbin=40else 01000001whenbin=41else 01000010whenbin=42else 01000011when bin= 43 01000100when bin=

27、44 01000101whenbin01000101whenbin=45else 01000110whenbin=46else 01000111whenbin=47else 01001000whenbin=48else 01001001whenbin=49else 01010000whenbin=50else 01010001whenbin=51else 01010010whenbin=52else 01010011whenbin=53else 01010100whenbin=54else 01010101whenbin=55else 01010110whenbin=56else 010101

28、11whenbin=57else 01011000whenbin=58else 01011001whenbin=59else end block seven_seg:block seg=0111111whennum=0 0000110whennum=1else 1011011whennum=2else 1001111whennum=3else 1100110whennum=4else 1101101whennum=5else 1111101whennum=6else 0000111whennum= 7 1111111whennum= 8 1101111when num = 9 else 111

29、0111whennum=10else 1111100whennum=1101111when num = 9 else 1110111whennum=10else 1111100whennum=11else 0111001whennum=12else 1011110whennum=13else 1111001whennum=14else 1110001whennum=15else endblockseven_seg; end a;3.1.2模塊實(shí)驗(yàn)波形仿真如圖3.1.1圖控電源各部分工作所需的12V 和+5V 電源由固定集成穩(wěn)壓器7812、7912、和7805 提到，但要求能提供2A 的電流。輸

30、出電壓反饋到NE5534 的輸入級的反向輸入端，當(dāng)同相輸入IN+和反向輸入端IN-3.2 24進(jìn)制代碼設(shè)計(jì)與仿真結(jié)3.2.124進(jìn)制源代碼 library ieee;use3.2 24進(jìn)制代碼設(shè)計(jì)與仿真結(jié)3.2.124進(jìn)制源代碼 library ieee;useuseuseentity counter24 end : :out std_logic_vector(5downto : : : : out architecturea ofcounter24 signalq:std_logic_vector(4downto0); signal rst, dly : std_logic;sif rst=

31、 q = elsifcpeventandcp=1then dly = q(4);ifec=1then q = q+1;end end end cy24 = not q(4) andrst=cy24 = not q(4) andrst=1whenq=24orclr=1else bin=(0&q)whens=1else end 3.2.2模塊實(shí)驗(yàn)波形仿真如圖3.2.1圖電路符號如圖3.2.2圖圖圖圖圖圖3.3 60進(jìn)制代碼設(shè)計(jì)與仿真結(jié)3.3.160進(jìn)制源代碼 library ieee;use3.3 60進(jìn)制代碼設(shè)計(jì)與仿真結(jié)3.3.160進(jìn)制源代碼 library ieee;useuseuseent

32、ity counter60 : :out std_logic_vector(5downto : : : : out end architecturea ofcounter60 signalq:std_logic_vector(5downto0); signal rst, dly : std_logic;sif rst= q = elsifcpeventandcp=1then dly = q(5);ifec=1then q = q+1;end end end cy60 = not q(5) andrst=cy60 = not q(5) andrst=1whenq=60orclr=1else bi

33、n = q when s= end 3.3.2模塊實(shí)驗(yàn)波形仿真如圖3.3.1圖電路符號如圖3.2.2圖圖圖3.4 去抖代碼設(shè)計(jì)與圖圖圖3.4 去抖代碼設(shè)計(jì)與仿真時鐘信號是分頻出來的一個1KHZarchitecture a ofdebunce signalle,dly,ndly,diff:count: signal q: std_logic_vector (14downto 時鐘信號是分頻出來的一個1KHZarchitecture a ofdebunce signalle,dly,ndly,diff:count: signal q: std_logic_vector (14downto d0 :

34、 sifcpeventandcp=1then d0 = q(14);q = end end sle = q(14) andnot endblockcount; debunce : blocksignal d0, d1, s,r: sif cpevent and if le = d1=d0;d0=key; s = d0 and d1;r=d1=d0;d0=key; s = d0 and d1;r=notd0andnotd1; end if;end end dly=rnorndly; ndly=snordly; dly_out = dly;endblockdebunce; wei: blocksi

35、gnal d1,d0 :sif cpevent and cp=1then d1=d0;d0=dly;end end diff=d0andnotd1; end block wei;dif_out=diff; end a;3.4.2模塊實(shí)驗(yàn)波形仿真如圖3.4.1圖電路符號如圖3.4.2圖圖圖圖電路符號如圖3.4.2圖圖圖社：社：作者作者作者作者.SOPC技術(shù)與應(yīng)用.：，2005.Vefilog ，2005作者作者 library useuseuseieee.std_logic_unsigned.all; entity newclock isport( endlibrary useuseuseiee

36、e.std_logic_unsigned.all; entity newclock isport( endstd_logic_vector(7downto std_logic_vector(5downto :instd_logic_vector(2 downtoarchitectureaofnewclockis component counter60port( end component;: : : : : std_logic_vector(5downto0); component port( end component;: : : : : std_logic_vector(5downto0)

37、; signal bin: signal dbs: signaldbm: signal dbh: signal enb: signal sec: signal bcd: signal clr:std_logic_vector(5downtostd_logic_vector(5downto std_logic_vector(5downtostd_logic_vector(5downto std_logic_vector(2downto0); std_logic_vector(7downto0); signal: signal s signalnum:std_logic_vector(2 down

38、to:std_logic_vector(3downtosignalseg signal sel signal s:std_logic_vector(6 downto:std_logic_vector(5 downto le, :signal s:std_logic_vector(1signalseg signal sel signal s:std_logic_vector(6 downto:std_logic_vector(5 downto le, :signal s:std_logic_vector(1downto0); signal match: std_logic;signal glit

39、ter: signalu1: counter60 port map(clk,dbs,enb(0),clr,ecs,cys); u2:counter60portmap(clk,dbm,enb(1),clr,ecm,cym); u3: counter24 port map(clk,dbh,enb(2),clr,ech,cyh); clr= not key(0);sc=e(1) and eadj=secand (not sc) andecs= (sec and sc) or (adj and se(1) and not secm= (cys and sc) or (adj and not se(1)

40、 and sech= (cym and sc) or (adj and not se(1) and not sselout= sel;gen:for iin 0to 6segout(i)=seg(i)and(scor(glitterornotmatch); end generate;segout(7)=0; end block conj; signalq:std_logic_vector(25downto0); dly,sdly : std_logic;sifclkeventandclk=1then dly= q(22);sdly=q(16); q= q+1;end end glitter=

41、sec=q(22)andnotdly; s= q(16 downto 14);sle= q(14) and notsel=000001when s=0 else 000010whens=1else 000100whens=2001000whens=3else 010000whens=4else 100000whens=5else enb=001when(s=0ors=1)001000whens=3else 010000whens=4else 100000whens=5else enb=001when(s=0ors=1)else 010when(s=2ors=3)else 100when(s=4

42、ors=5)else bin= dbs when enb=001else dbmwhenenb=010else dbh when enb=100else match=1when(s=0ors=1)ands 1when(s=2ors=3)ands 1when(s=4ors=5)ands endblockfdiv; sel_bcd:block e=10)else e=01)else e=00)num=bcd(3downto0)when(s=0ors=2ors=4)else bcd(7 downto 4);endblocksel_bcd; settime : blocksignalq:std_log

43、ic_vector(2downto0); signal set,ec : std_logic;sif elsifclkeventandclk=1then if ec=1thenendif; end if;end set=1whenq=7else ec=nd e=q(1downto0); end block settime;key_d: signald0,d1,s,r,dly,ndly:std_logic; sifclkeventandclk=1then if sd1=d0;sifclkeventandclk=1then if sd1=d0;d0=key(2); s= d0 and d1;r=n

44、otd0andnotd1; end if;end end dly=rnorndly; ndly=s nor dly; dly_out= dly;endblockkey_d; wei: blocksignald1,d0:std_logic; sif clk event and clk=1then d1=d0;d0=dly_out;end end diff=d0andnotd1; end block wei;bin_bcd:block bcd=00000000when bin = 0 else 00000001when bin = 1 else 00000010when bin = 2 else

45、00000011when bin = 3 else 00000100when bin = 4 else 00000101when bin = 5 else 00000110when bin = 6 else 00000111when bin = 7 else 00001000when bin = 8 else 00001001when bin = 9 else 00010000whenbin=10else 00010001whenbin=11else 00010010whenbin=12else 00010011whenbin=13else 00010100whenbin=14else 00010101whenbin=15else 0001