數(shù)電數(shù)字電路中不僅需要對(duì)信息進(jìn)行運(yùn)算和處理還

Combinational

circuit(組合電路):Basic

unit

—

Logic

gate

—

No

memory

function數(shù)字電路中，不僅需要對(duì)信息進(jìn)行運(yùn)算和處理，還需要將運(yùn)算結(jié)果保存起來(lái)，需要

功能的邏輯單元。Sequential

circuit（時(shí)序電路）:

Basic

unit

—

FF

—

MemoryChapter

5Latch/Flip-Flop鎖存器/觸發(fā)器1a)

Bistable(雙穩(wěn)態(tài)):1

and

0FFDefinition

of

FF:

memory

elementIt

can

store

one

bit

of

binary

information,it

is

also

called

Latch

(鎖存器)能

一位二進(jìn)制信息的基本單元。b) Set

1, Set

0c) Keep

new

state

after

the

signal

disappear23電路的兩種穩(wěn)態(tài)都可以保持，因此稱(chēng)為雙穩(wěn)態(tài)電路。11G2雙穩(wěn)態(tài)

單元電路邏輯狀態(tài)分析：若初始狀態(tài)Q=0，由于非門(mén)G2，使Q=1；Q=1反饋到G1，又保證Q=0，電路自行保持在Q=0，Q=1狀態(tài)，形成“0”穩(wěn)態(tài)；若初始狀態(tài)Q=1，則Q=0，則形成另一種穩(wěn)態(tài)（“1”穩(wěn)態(tài)）；QQG14Two

cross-coupled

NAND

gatesInputs:S

Set

置位端R

Reset

復(fù)位端Output:

Q=1,

Q

=0

“1”

態(tài)

HighQ=0,

Q

=1

“0”

態(tài)

LowDefinition:

The

state

of

a

Latch/FF

is

Q定義：觸發(fā)器狀態(tài)是Q狀態(tài)§5.1

基本RS觸發(fā)器(Basic

RS-Latch)QG1G2&&SRQ1.

電路結(jié)構(gòu)Circuit5.1.1

與非門(mén)構(gòu)成的基本RS觸發(fā)器(NAND

gates

Basic

RS-Latch)IEEESymbol2.

Operation

(state

~

input)G1

locked,1)

S

=0,

R

=1If

S

converts

to

1,S=

R

=

1 Keep

the

state:

No-change

(NC)FF

remains

in

present

state

（memory

function)Q=1,

Q=0

Set

(置1）0R

11because

Q

=

0,

G1

locked,

Q

=

11QG1G2&&Q0SSR52)

S

1,R

0No-change

Q

=

0G2

lockedQ

=

1,

Q

=

00

QIf

R

converts

to

1,Q

=0,

G2

lockedS=

R

=

11Truth

tableSRstate00011

0Set

(1)100

1Reset

(0)11NC

NCNo-

changeReset

(置0)&&Q

11

S

0RG1G263)

S

=0,R

=

0Q

and

Q

Forced

HighForbidden

state

（Q

=

1

Q

=

1(強(qiáng)制為邏輯高）狀態(tài)）when

R,

S

simultaneously

0

1propagation

delay

time

tpd011SRstate001

1Forbidden:S

R

0→1同時(shí)Set

(1)Reset

(0)No-

change011

0100

111NC

NC11都是穩(wěn)定狀態(tài)，但不知是哪種.

在S

R

同時(shí)從0變到1時(shí)，狀態(tài)不定&&S

0RG1G2tpd1

>tpd2

(G2Q

=

0fast)Q

=

1tpd1

<

tpd2(G1

fast)Q

=

0 Q

=

175.1.2

Function

Descriptions

of

RS-Latch基本RS觸發(fā)器邏輯功能描述方法電路的下一個(gè)穩(wěn)定狀態(tài)(次態(tài))Qn+1

與觸發(fā)器現(xiàn)在的穩(wěn)定狀態(tài)(現(xiàn)態(tài))

Qn

以及現(xiàn)在的輸入信號(hào)(RS-FF為

R

,

S

)的邏輯關(guān)系描述方法：Truth

table

狀態(tài)轉(zhuǎn)移真值表（狀態(tài)表）State

equation

(Characteristic

equation)狀態(tài)方程（特征方程）State

diagram

and

State

table

狀態(tài)轉(zhuǎn)移圖和激勵(lì)表Waveforms

(Timing

diagrams)

波形圖（時(shí)序圖）81．狀態(tài)轉(zhuǎn)移真值表(狀態(tài)表)(Functional

table)Truth

tableRSQnQn+1010001101001101111001111000不確定001不確定&&SRG1G2Description

the

function

of

a

basic

RS-LatchRSQn+101010111Qn00不確定9Qn00

01

11

102．狀態(tài)方程State

equation

(Characteristic

equation)Qn+1

R

S01

ΦΦ0

1110

0State

equation

(Characteristic

equation)Qn1

S

RQn

S

R

1不同時(shí)為0注意：將R

和S

看作整體輸入信號(hào)符號(hào)上面的橫線表示低電平有效RSQnQn+1010001101001101111001111000不確定001不確定10113.

狀態(tài)轉(zhuǎn)移圖State

diagram

and

State

table用圖形表示輸出狀態(tài)轉(zhuǎn)換的條件和規(guī)律State

diagramDescribe

state

conversion

and

conversing

condition.Combinational

circuit:

Truth

table

–輸入輸出間關(guān)系Sequential

circuit:State

diagram

–狀態(tài)轉(zhuǎn)換及轉(zhuǎn)換條件QnQn

101condition狀態(tài)，代碼轉(zhuǎn)換(從原狀態(tài)指向新?tīng)顟B(tài))010/00/01/01/1conditionX/Z

conversion

conditionX/Z12激勵(lì)表狀態(tài)轉(zhuǎn)移激勵(lì)輸入Qn

→Qn+1RS00Φ101101001111Φ激勵(lì)表列出已知狀態(tài)轉(zhuǎn)換和所需要的輸入條件的表稱(chēng)為激勵(lì)表。激勵(lì)表是以現(xiàn)態(tài)

Qn和次態(tài)

Qn+1為變量，以對(duì)應(yīng)的輸入

R

S

為函數(shù)的關(guān)系表.表示出在什么樣的激勵(lì)下，才能使現(xiàn)態(tài)Qn

轉(zhuǎn)換到次態(tài)Qn+1.Qn+1QnRSQnQn+1010001101001101111001111000不確定001不確定狀態(tài)表134.

波形圖Timing

Diagrams(Waveforms)QQSR01100uncertainSRstate001

1S

R

0→1不定Set

(1)

S≠RReset

(0)

Q=RNo-

change011

0100

111NC

NCDetermine

the

output

waveform

corresponding

to

the

inputwaveform. (initially

Q

=

0)VtForced

High(強(qiáng)制為邏輯高）Q≥1≥1QRS5.1.3

或非門(mén)構(gòu)成的基本RS觸發(fā)器N ates

RS-LatchSRQn+100Qn01010111不確定ForbiddenInputs

S,R:

高電平有效Active-

High狀態(tài)表Truth

table

of

Nates

RS-LatchQuestion：一個(gè)與非門(mén)和一個(gè)或非門(mén)能否構(gòu)成觸發(fā)器？142.

邊沿觸發(fā)利用時(shí)鐘上升、下降沿作為觸發(fā)信號(hào)Rising

edge

(Positive

edge)Falling

edge

(Negative

edge)§5.2 Gated

FF

（時(shí)鐘觸發(fā)器/同步觸發(fā)器）在數(shù)字系統(tǒng)中，經(jīng)常要對(duì)各部分電路進(jìn)行協(xié)調(diào)，以動(dòng)作，使得電路在控制信號(hào)（時(shí)鐘）作用下同時(shí)響應(yīng)輸入信號(hào)及狀態(tài)變化，即同步。1.

電平觸發(fā)利用時(shí)鐘高、低電平作為觸發(fā)信號(hào)15Add

G3、G4

to

the

basicRS-FF,

onlywhenCLK=1, G3

and

G4

open.WhenCLK=0, G3

and

G4

locked.Discuss

the

situation

of

CLK=1CLK=1時(shí)的FF狀態(tài)G1G3G2G4CLK

R＆＆＆＆S5.2.1Synchronous

RS-FF(同步RS觸發(fā)器)16changeQn+1=QnS

R

QnQn+1Comments0000S=R=00011Qn+1=Qn01000110R≠S1001Qn+1=S1011110φR=S=1,=1111φS

R

1

→0

φSRFF

state0010101

11

00

1S

R

0→1不定

Set

(1)Reset

(0)No-

change11NC

NCCLKS=R=0

G3=1,G4=1

FF

noR＆＆＆＆SG3RG4SSynchronous

RS-FFTruth

tableS=0,

R=1Qn+1=0S=1,

R=0G3=1,G4=0G3=0,G4=1Qn+1=1S=1,

R=1

G3=G4=0,

=1S

and

R

1→0,

Q

uncertain17Characteristic

equation

of

RS-FF同步RS-FF特征方程SymbolSCLK

R00

01

11

1001Qn+1QnSR00Ф110Ф1Relationship

between

output

and

input（不同時(shí)為1）Disadvantage:

Uncertain

state缺點(diǎn)：存在不確定狀態(tài)Qn+1

=

S

+

RQnS?R

=

0185.2.2 Synchronous

D-FF

(同步D-FF)Characteristic

equation

ofgated

D-FF

:Qn+1

=

DDSymbols1&&&&CLKSRNOT

gate

in

between

S

and

RS≠ROperation:CLK=0,

FF

no

changeCLK=1,

FF

workD=1,

(S=1,

R=0) Qn+1

=

1D=0,

(S=0,R=1) Qn+1=

0S=D,

R=

Dno

uncertain

state無(wú)不確定狀態(tài)DCLK195.2.3 Synchronous

JK-FF（同步JK-FF

）JKQnQn+1comments0000J=K=00011Qn+1=Qn01000110J≠K1001Qn+1

=

J10111101J=K=11110Qn+1=QnAdd

two

feedback

lines

to

inputsS

JQn

,

R

KQnQ,

Q

不同時(shí)為1，RS不同時(shí)1→0no

uncertain

state

無(wú)不確定狀態(tài)&&CLK&&1

1

0J

K0

0110111

01

0

11

1

00

1

01

0

0Two

inputs:

J,

KCLK

=0,

stop; CLK=1,

work20Characteristic

equation

of

JK-FF:可從RS-FF

方程推出Qn1

S

RQnn

JQ

KQnQn

JQ

n

KQnSymbol:Qn+100

01

11

1001QnJK00111001Qn+1

=

JQn

+

KQnJ21CLKKJK-FF

激勵(lì)表0

1State

diagram

of

JK-FFJ

1,K

J

,K

1J

K

0J

0K

狀態(tài)轉(zhuǎn)移

Qn

→Qn+1激勵(lì)輸入

J

K000Φ011Φ10Φ111Φ0JKQnQn+10000001101000110100110111101111022State

table5.2.4 Synchronous

T-FF（同步T-FF）J

=

K

=

TTCharacteristic

equation

of

T-FF:Qn1

TQn

TQn

T

QnT=0,T=1,Qn1

QnQn1

QnTCLKKJCLKno

changeturn

over235.2.5

同步觸發(fā)器缺點(diǎn)The

Disadvantage

of

Synchronous

FFDuring

CLK=1, FF:

trigger

stateQn+1changes with

inputs

of

R,

S,

D,

J,

K,

TCLKDQGated

FF

都存在空翻問(wèn)題要克服，用新結(jié)構(gòu)出現(xiàn)空翻空翻：Q

changes

more

than

one

time

in

one

CLK

period.一個(gè)CLK周期內(nèi)，Q

端只能變化一次，變化一次以上稱(chēng)FF

的空翻。0Qn+1

=D24§5.3Master-Slave

Edge-Triggered

FF(主從結(jié)構(gòu)邊沿觸發(fā)器)為了克服

FF

的空翻，出現(xiàn)了邊沿

FF原理都是：邊沿觸發(fā)

edge

-

triggeredFF

changes

states

at

clock

pulseedgepositive

edge

(rising

edge)

negative

edge

(falling

edge)邊沿到來(lái)的瞬間觸發(fā)，縮短觸發(fā)時(shí)間，降低錯(cuò)誤Master-Slave

FF

is

one

of

them主-從結(jié)構(gòu)觸發(fā)器是邊沿觸發(fā)器的一種255.3.1

Master-Slave

RS-FF

主從RS觸發(fā)器Two

same

synchronous

RS-FFs兩個(gè)同步RS-FFAn

NOT

gate

between

2CLKs非門(mén)連接時(shí)鐘信號(hào)(one

FF

work,

another

stop)Q’＆＆＆＆＆＆＆＆R1S

CLKThe

state

of

Slave

FF

Q

is

thestate

of

FFThe

output

of

Master

FF

is

Q’SlaveFF

從MasterFF

主∵Q’

no

change∴Q

no

change∴Q

no

changeCLK=0,

M

-

FF

stop,

Q’

no

changeCLK

=1,

Slave

open

,CLK=1,

M-

FF

open,

S,R→

Q’CLK

=0,

Slave

FF

stop26∴During

CLK=0

and

CLK=1,

Q

no

changeR≠SQn+1=SAt

the

moment

of

CLK

goes

from

1

to

0

(CLK

falling

edge),the

information

in

Master

FF

transmits

to

Q時(shí)鐘下降沿，改變Q狀態(tài)∴Master-Slave

RS-FFis

CLK

falling

edge

triggered

FFQ

is

relevant

to

the

last

information

prior

to

CLK

active-edgeCLKSRQ’Q0空翻01從-FF無(wú)空翻，Q

無(wú)空翻275.3.2

Master-Slave

JK-FF

主從JK觸發(fā)器&&&&&&&&1Two

feedback

lines

on

Master-SlaveRS-FF

form a

Master-SlaveJK-FFTruth

tableCharacteristics

equationsame

asgated

JK-FFJ

KCLKQn+1J

K1.Qn

J=K=0,保持2.

0

J≠K,

Qn+1=

J1

0

11

1

Qn

J=K=1,翻轉(zhuǎn)Qn+1

=

JQn

+

KQnMaster-Slave

JK-FF

is

a

qualified

product:

無(wú)空翻，無(wú)狀態(tài)不定28Function

descriptionMaster-Slave

JK-FF

is

triggered

at

CLK

negative

edge.主從JK-FF是時(shí)鐘下降沿觸發(fā)Before

CLK

negative

edge

comesQn+1

=

QnQn+1

=

JIf J

=

K=

0If J

≠

KIf J

=

K=

1do

not

consider

Q’CLKCLKCLKQn+1

=

QnQn

為有效邊沿前的最后信息29SymbolQ,

J

→

same

sideQ,

K

→

same

sidePractice2345

1CLKJKQInitially

Q=0waiting

forfalling

edgeJ

≠

K1J=K=0J=K=1JCLK

K1J C1

1KIEEE305.3.3

Direct

Input

of

JK

FF

（異步置0置1

JK觸發(fā)器）FFSynchronous

inputs

signal:

CLK,

J,

K,

D,

T,

R,

SAsynchronous

inputs

signal:

Direct

inputsDirect

set

input(set

1)S

DforceRDDirect

reset

input(set

0)SD&&&&&&&&1JKCLKRD3132Direct

inputs

force

the

state

of FF,

they

haveabsolu y

priority,

independent

of

J,

K,

CP直接輸入端，具有絕對(duì)優(yōu)先級(jí)ct

set

1ct

clear(清0)S

DRDCLK

J K

QnQn101φ

φφφ1

S

D

dire0

RD

direFF

worksNot

allowed10φ

φφφ1100Active

-

lowQn+1

=

JQn

+

KQnSD

RD

1JKCLKS

D

1JS

DRDC1

1KRDQ,

J,

SD→

same

sideDQ,

K,

R

→

sameside236SDRDJKQPracticeCLK

1000異步優(yōu)先沿不起作用45沿前是異步,優(yōu)先無(wú)SD,RD

波形時(shí)，SD

=RD

=1JKCLKS

DRD335.3.4 Direct

Input

D-FFM/SJK-FF

add

a

NOT

gate:Characteristic

equationQ

n

1

DS

R

1D

DD

CLK1DD-FF

是JK-FF

中J≠K

的部分，是JK-FF

的特例JKCLK3435Practice

1CLKSDRDDQ2345Before

CLK

falling

edge,

D=0

(D=1),

theafter

CLK

falling

edge

comesQn+1

=0

(Qn+1

=1),Qn+1

delays

one

period

of

CLKDelay

FF（延時(shí)觸發(fā)器）

0

10100沿前強(qiáng)制5.3.5

Direct

Input

T-FFQn1

TQ

n

TQ

n

T

QnSD

RD

1CLK

falling

edge

triggeredT=0,T=1,Qn1

QnQn1

QnT-FF

是JK-FF

中J=K

的部分，是JK-FF

的特例Toggle

–

FF(反轉(zhuǎn)觸發(fā)器)J

=

K

=

TTCharacteristic

equation

of

T-FF:KCLKJTCLK36§5.4

Positive

Edge-Triggered

FF上升沿觸發(fā)器/維持－阻塞式正常工作時(shí)要求Master-Salve

JK-FF

在CLK＝1期間J,K

信號(hào)不變，但干擾信號(hào)仍能進(jìn)入。改進(jìn)Positive

edge

triggeredCLK37CLKS

DRD5.4.1

Positive

Edge

Trigger

D-FF1&&

2&

45&&6D通過(guò)G6、G5

等在G3、G4When

CLK

positive

edge

comesCLK=0,

G3=G4=1,

Q

no

changeCLKIf

D=0,106

5G

=1,

G

=0,G3=1,

G4=0,If

D=1, G6=0,

G5=1,0

11

03&∴Q=00

1D0

1Qn+1=

D維持－阻塞式Operation

:∴

Q=1(S

D

RD

1)G3=0,

G4=1,38維持－阻塞式FF

在CLK

上升沿觸發(fā)(P107)CLK上升沿前D的數(shù)據(jù)為CLK上升沿到時(shí)Qn+1

的狀態(tài)CLKDQSymbol

:DCLKS

DRDPositive

edge

triggeredQn+1

=DFF39Example:

畫(huà)出上升邊沿觸發(fā)的D-FF波形CLKRDS

DDQ畫(huà)波形圖步驟Waveform

stepsCharacteristicequationCLK

active

edge01forceDirect

inputsRDS

DQn+1

=

DQn+1

=

JQn+KQnQn+1

=

T⊕Qn495.4.2

Positive

Edge

Triggered

JK-FFSymbol

:It

is

as

same

as

Master-Slave

JK-FF, except

betriggered

at

CLK

positiveedge.RDS

DJ

CLK

KQn1

JQn

KQnSD

RD

1J

KQn+1Qn

J=K=0,保持0

J≠K,

Qn+1=

J1

0

11

1

Qn

J=K=1,翻轉(zhuǎn)41425.4.3

Positive

Edge

Triggered

T-FFSymbol

:Qn1

T

QnSD

RD

1CLK

positive

edge

triggeredS

DRDT

CLK6

kinds

of

qualified

products:Negative

edge

triggered

JK-FF,

D-FF,

T-FFPositive

edge

triggered

JK-FF,

D-FF,

T-FF請(qǐng)大家不要誤認(rèn)為JK觸發(fā)器就一定是主從結(jié)構(gòu)或負(fù)邊沿觸發(fā)觸發(fā)器的分類(lèi)結(jié)構(gòu)：基本時(shí)鐘（同步）主從異步（Rd,

Sd）維持阻塞外部特性（邏輯功能）：RS-FFJK-FFD-FF（Delay

FF

）T-FF（Toggle

FF

）觸發(fā)方式：電平觸發(fā)：active

High,active

Low邊沿觸發(fā)：Positive

(Rising),Negative(falling)43Practice:分別畫(huà)出上升沿及下降沿觸發(fā)的JK觸發(fā)器波形Draw

waveforms

of

positive

and

negative

triggeredJK-FF,respectively.QNegative1

2

3

4

5

6CLKRDS

DJKQPositive004445§5.6 Applications

of

FFQn1

T

QnCircuit:

Frequency

divided-by-2

device二分頻電路12QC

L

Kff

T=1,Qn+1=QnExample

1:Apply

the

CLK,

RD

,

T

waveforms

to

the

FF

of

Fig

1.Determine

the

Q

waveform.CLKRDTQS

DRDTCLK0TCLKTQTQ

=

2TCLKToggle

FF

翻轉(zhuǎn)Example

2:For

the

circuit

in

the

follow

figure,

determine

the

Q

waveform

tothe

input

waveforms.Driving

circuitD

=

ABDCLK＆A

BCLKRDS

DABDQQn+1

=

D46Example

3：Determine

the

Q1and

Q2

waveforms

relative

to

CLK

andK1

waveforms

in

the

following

circuit.

Assumethat

Q1

and

Q2

are

initially

high.11Qn1

Qn1

1

K

QnCLKK1Q1Q2Q2

T2

Q1

J1

1Q2

K1CLK1T2

=

Q

n2Q2n+1

=

T2⊕Q

n1

2=

Q

n⊕Q

n47Example

4.For

the

following

circuit,

determine

the

Q1

andQ2

waveforms

relative

to

CLK

and

K1

waveforms,assuming

that

Q1=Q2=0

initially.RDCLKK1Q1Q21Qn1

Qn1

1

1

K

QnCP1Q2

D21K1Q

J1Q2Q2n+1

=

D2

=

Q1nD2

1When

Q

=1,

R

=0,

Q

=04849§5.5

Conversion

Between

FFsGiven

FF:FF:Qn1

JQn

KQnQn1

DAdd

a

NOT

gate觸發(fā)器相互轉(zhuǎn)換1.

Convert

JK-FF

to

D-FFJKCLK1D

n

nn

nJQ

KQ

D

(Q

Q

)

DQn

DQn∴

J=D,

K=

DDCLK2.

Convert

JK-FF

to

T-FFGiven

FF:FF:Qn1

JQn

KQnQn1

T

Qn

TQn

TQnJ

=

K

=

TJKCLKS

D

RDS

DRDTCLKT503.

Convert

T-FF

to

D-FFGiven

FF:Qn1

T

QnQn1

DFF:S

DRDTCLKT⊕Qn

=DT

=

D⊕QnD=1514.

Convert

T-FF

to

JK-FFGiven

FF:Qn1

T

QnQn1

JQn

KQnFF:T

Qn

JQn

KQnConvert

D-FF

to

JK-FFConvertD-FF

to

T-FFnT

(JQ

KQn

)

Qn

JQ

n

KQn≥1&&JKTCLK5253s:85.195.2054Difference

between

Latch

and

Flip-flop(鎖存器與觸發(fā)器區(qū)別)Latch鎖存器是對(duì)電平敏感的電路，在一定電平作用下改變狀態(tài)。例如，