(完整版)EDA期末考試題A卷

嘉應(yīng)學(xué)院電子信息工程學(xué)院考試題樣題（A卷）_Ｃ。年6卷號座名姓班系……………封……………密……………線……………封……………密……………題號一二三四五得分在=．/）./==7....．。....。．D）AA...D.Ｄ））硬；第.固；一軟；頁.共四頁..4LIBRARY__ＩＥＥＥ________;1LIBRARYIEEE;USEIEEE.________STD_LOGIC_1164_____________.ALL;2USEIEEE.STD_LOGIC_1164.ALL;3ENTITYcoderIS4ENTITYCNT4ISPORT(din:INSTD_LOGIC_VECTOR(____9DOWNTO0________________);號座名姓班系……………封……………密……………線……………封……………密……………output:_____OUT_____STD_LOGIC_VECTOR(3DOWNTO0));ENDcoder;ARCHITECTUREbehavOF________CODER_____ISSIGNALSIN:STD_LOGIC_VECTOR(3DOWNTO0);BEGINBEGINPROCESS(_____DIN______)IF(din(9)='0')THENSIN<="1001";ELSIF(din(8)=’0’)_________________THENSIN<="1000";ELSIF(din(7)='0')THENSIN<="0111";ELSIF(din(6)='0')THENSIN<="0110";ELSIF(din(5)='0')THENSIN<="0101";ELSIF(din(4)='0')THENSIN<="0100";ELSIF(din(3)='0')THENSIN<="0011";ELSIF(din(2)='0')THENSIN<="0010";ELSIF(din(1)='0')THENSIN<="0001";ELIN<=“0000”______________;ENDIF___________ENDPROCESS；__Output<=sin_____________；ENDbehav;在1第二頁共1四頁235PORT(CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCNT4;ARCHITECTUREbhvOFCNT4ISSIGNALQ1:STD_LOGIC_VECTOR(3DOWNTO0);CIN:INSTD_LOGIC;COUT:OUTSTD_LOGIC;S:OUTSTD_LOGIC_VECTOR(7DOWNTO0));678910BEGIN11PROCESS(CLK)BEGIN12IFRISING_EDGE(CLK)begin13IFQ1<15THEN14Q1<=Q1+1;15ELSE16Q1<=(OTHERS=>'0');17ENDIF;18ENDIF;19ENDPROCESS;20Q<=Q1;21ENDbhv;228BSLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYADDER8ISPORT(A,B:INSTD_LOGIC_VECTOR(7DOWNTO0);ENDADDER8;ARCHITECTUREONEOFADDER8ISSIGNALTS:STD_LOGIC_VECTOR(8DOWNTO0);BEGINTS<=(‘0’&A)+(‘0’&B)+CIN;S<=TS(7DOWNTO0);COUT<=TS(8);INPUTaDFFORin_a=“00”DFFin_a=“01”號座名姓班系QDQOUTPUT…DINPUT…………in_a/=“00”st1st0out_a<=“0101”;out_a<=“1000”;in_a=“11”封LIBARRYIEEE;…USEIEEE.STD_LOGIC_1164.ALL;ENTITYMYCIRISPORT(XIN,CLK:INSTD_LOGIC;YOUT:OUTSTD_LOGIC);ENDMYCIR;in_a/=“11”in_a/=“01”…………密……………線……………封……………密……st3st2ARCHITECTUREONEOFMYCIRISSIGNALA,B,C;BEGINin_a/=“11”out_a<=“1101”;out_a<=“1100”;B<=XINORA;PROCESS(CLK)BEGINin_a=“11”IFCLK’EVENTANDCLK=‘1’THENA<=C;圖a狀態(tài)圖C<=B;ENDIF;ENDPROCESS;YOUT<=C;圖b狀態(tài)機結(jié)構(gòu)圖…第三Libraryieee;……頁Useieee.std_logic_1164.all;共Entitymoorebis四Port(clk,reset:instd_logic;頁Ina:instd_logic_vector(1downto0);Outa:outstd_logic_vector(3downto0));Endmooreb;ArchitectureoneofmoorebisTypems_stateis(st0,st1,st2,st3);Signalc_st,n_st:ms_state;BeginProcess(clk,reset)BeginIfreset=‘1’thenc_st<=st0;；=’……………封……號……座…密……………線…名……姓……封…班…………密系……………Endif;Endprocess;Process(c_st)BeginCasec_stisWhenst0=>ifina=“00”thenn_st<=st0;Elsen_st<=st1;Endif;Outa<=“0101”;Whenst1=>ifina=“00”thenn_st<=st1;Elsen_st<=st2;Endif;Outa<=“1000”;Whenst2=>ifina=“11”thenn_st<=st0;Elsen_st<=