CMOS制造工藝流程簡介

2.1

CMOS制造工藝流程簡介

We

will

describe

a

modern

CMOS

process

flow.Process

described

here

requires

16

masksand

>

100

process

steps.1第二章CMOS制備基本流程StagesofICFabrication2?

In

the

simplest

CMOS

technologies,

we

need

to

realizesimply

NMOS

and

PMOS

transistors

forcircuits

like

those

illustrated

below.CMOS

Digital

Gates反相電路或非門：同時(shí)輸入低電平時(shí)才能獲得高電平輸出3PMOS

and

NMOSwafer

crosssection

afterfabrication2-Level

Metal

CMOS兩層互連布線的CMOS4有源器件（MOS、BJT等類似器件），必須在外加適當(dāng)?shù)钠秒妷呵闆r下，器件才能正常工作。對于MOS管，有源區(qū)分為源區(qū)和漏區(qū)，在進(jìn)行互聯(lián)之前，兩者沒有差別。????????Choosing

a

SubstrateActive

RegionN

and

P

WellGateTip

or

ExtensionSource

and

DrainContact

and

Local

InterconnectMultilevel

MetalizationProcessing

Phases51

μmPhotoresist40

nmSiO2Choose

the

substrate(type,

orientation,resistivity,

wafer

size)?

Initial

processing: -

Wafer

cleaning -

thermal

oxidation,

H2O

(≈

40

nm,

15

min.

@

900oC) -

nitride

LPCVD(低壓化學(xué)氣相沉積)

(≈

80

nm@

800oC)?

Substrate

selection:-moderately

high

resistivity(25-50

ohm-cm)-(100)

orientation-P-

type.80

nmSi3N4Choosing

a

SubstrateSi,(100),PType,25~50Ωcm1st

Mask

Photoresist

?

spinning

and

baking@

100oC(≈

0.5

-

1.0

μm)62.2有源區(qū)的形成?

Photolithography-Mask

#1

pattern

alignmentand

UV

exposure-Rinse

away

non-pattern

PR-Dry

etch

the

Nitride

layer--Plasma

etch

with

FluorineCF4

or

NF4

Plasma-Strip

Photoresist(H2SO4或O2plasma)Active

Area

Definition(主動區(qū))SiO2Si3N4Photoresist7?

Wet

Oxide

(thick

SiO2)-

H2O

(≈

500

nm,90min.

@1000oC)?

Strip

Nitride

layer

-

Phosophoric

acid(磷酸)

orplasma

etch，選擇性問題Field

Oxide

Growth

-

LOCOS:

Local

Oxidation

ofSilicon(局部硅氧化工藝)SiO2Si3N4?

薄的SiO2層，厚的Si3N4層，避免鳥喙(bird’sbeak)的影響8?場區(qū):很厚的氧化層，位于芯片上不做晶體管、電極接觸的區(qū)域，可以起到隔離晶體管的作用。?

Photolithography(套刻)-

Mask

#2

pattern

alignmentand

UV

exposure?

IonImplantation離子注入

-

B+

ion

bombardmentPenetrate

thin

SiO2

and

fieldSiO2

--反型：半導(dǎo)體表面的少數(shù)載流子濃度等于體內(nèi)的多數(shù)載流子濃度時(shí)，半導(dǎo)體表面開始反型。-

150-200keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentrationP-well

Fabrication?

Strip

Photoresist-

Rinse

away

non-pattern

PR2.3N阱和P阱的形成SiO2Photoresist9?

Ion

Implantation

-

P+

ion

bombardment-

Penetrate

thin

SiO2

and

field

SiO2-

300-400keV

for

1013cm-2

--

Implantation

Energy

andtotal

dose

adjusted

fordepth

and

concentration?

Strip

PhotoresistN-well

Fabrication?

Photolithography

-Mask

#3

pattern

alignmentand

UV

exposure-

Rinse

away

non-pattern

PR10?ThermalAnneal(熱退火火)-Repaircrystallatticestructuredamageduetoimplantation?DryFurnace(N2ambient，防止止氧化化層生生成)-Anneal30min@800?CorRTA(快速熱熱退火火)10sec@1000??C-Drive-in4-6hours@1000?C-1100?CThermalAnnealandDiffusion?NandPDrive-in(擴(kuò)散推推進(jìn))-Thermaldiffusionofdopanttoshallowerthandesireddepth--Drive-inisacumulativeprocess!11?Photolithography-Mask#4patternalignmentandUVexposure-Rinseawaynon-patternPR-B+ionbombardment-50-75keVfor1-5×1012cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentration?StripPhotoresistThresholdAdjustment,P-typeNMOS?IonImplantation2.4柵電電極極的的制制備備開啟啟電電壓壓調(diào)調(diào)整整12調(diào)整整之之前前P阱的的摻摻雜雜濃濃度度調(diào)整整時(shí)時(shí)的的注注入入劑劑量量ThresholdAdjustment,N-typePMOS?Photolithography-Mask#5patternalignmentandUVexposure-Rinseawaynon-patternPR-As+ionbombardment-75-100keVfor1-5×1012cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentration?StripPhotoresist?IonImplantation13?Removeexistinggateregionoxide?FurnaceSteps-ThermalAnneal-Oxidegrowth3-5nm--O2ambient--0.5-1hour@800°CGateOxideGrowth柵極氧氧化層層生長長-HFetch，具有有良好好的選選擇性性--DryFurnace(N2ambient)--30min@800?C14?LPCVDDepositionofSi-Silane硅烷?AmorphousorpolycrystallinesiliconlayerresultsIonImplantation-P+orAs+(N+)implantdopesthepoly(typically5×1015cm-2)PolysiliconGateDeposition?0.3-0.5umSiO2多晶硅薄膜膜15熱分解?Photolithography-Mask#6patternalignmentandUVexposure?PlasmaEtch-Anisotropicetch各向異性蝕蝕刻--Verticaletchratehigh--LateraletchratelowGatePatterning（柵極的圖形形化）-Rinseawaynon-patternPR?Clorine(氯)orBromine(溴)basedforSiO2selectivity16目標(biāo)：NMOS器件中的N-注入?yún)^(qū)PMOS器件中的P-注入?yún)^(qū)多晶硅柵的的兩側(cè)形成成側(cè)壁隔離離層的薄氧氧化層2.5前端或延伸伸區(qū)(LDD)的形成17LDD:?LightlyDopedDrain(輕摻雜漏)?Reduceshortchanneleffectsduetogatevoltagemagnitudesandelectricfields?SourceandDrainmustbelayeredasNMOS:N+N-PorPMOS:P+P-NExtension(LDD)FormationNMOS?Photolithography-Mask#7patternalignmentandUVexposure-Rinseawaynon-patternPR-P+ionbombardment-50keVfor5×1013cm-2?StripPhotoresist?IonImplantation18?Photolithography?Mask#8patternalignmentandUVexposure?Rinseawaynon-patternPR?IonImplantation?B+ionbombardment?50keVfor5×1013cm-2?StripPhotoresistExtension(LDD)FormationPMOS19SiO2隔離介質(zhì)層CVDorLPCVDDepositionofSiO2?SilaneandOxygenOr0.5um?Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition20?Photolithography?Mask#6oversizedpatternalignmentandUVexposure?Rinseawaynon-patternPR?Verticaletchratehigh?Lateraletchratelow?StripPhotoresistAnisotropicSpacerEtch?PlasmaEtch?Anisotropicetch?Flourinebased21?ScreenOxideGrowth?ThinSiO2layer~10nmtoscattertheimplantedions?Photolithography?Mask#9patternalignmentandUVexposure?Rinseawaynon-patternPR?IonImplantation?As+ionbombardment?75keVfor2-4×1015cm-2?StripPhotoresistNMOSSourceandDrainImplant2.6源漏區(qū)的形成成Arsenic?Reducechanneling22?Photolithography?Mask#10patternalignmentandUVexposure?Rinseawaynon-patternPR?IonImplantation?B+ionbombardment?5-10keVfor1-3×1015cm-2?StripPhotoresistPMOSSourceandDrainImplant23?N+andP+Drive-in?Thermaldiffusionofdopanttoshallowerthandesireddepth?Drive-inisacumulativeprocess!?DryFurnace(N2ambient)?Anneal30min@900?CorRTA60sec@1000?C-1050?CTransientEnhancedDiffusion(TED瞬態(tài)增強(qiáng)擴(kuò)擴(kuò)散)?HigherthannormaldiffusivityduetocrystaldamageThermalAnnealing?ThermalAnneal?Repaircrystallatticestructuredamageduetoimplantation242.7接觸與局部部互聯(lián)的形形成ContactsandInterconnects?Titaniumsputteringlocalcontacts?ConformalCoatwithSiO2?Planarization?TungstenPlugvias?AluminumMetalDeposition?Repeat–Coat–Planarize–Plug–Metaldeposition25?HFetchtoremovethinSiO2?Removescreenoxidefromdrain,sourceandploygateregions?Dip(浸)forafewsecondswithHFContactOpeningsLDDandSidewallstructure?NMOS:LateralN+N-PN-N+?PMOS:LateralP+P-NP-P+26TitaniumDeposition?Tiisdepositedbysputtering(typically100nm).?TitargethitwithAr+ionsinavacuumchamber?TheTiisreactedinanN2ambient?FormsTiSi2andTiN(typically1min@600-700?C).?TiSi2hasexcellentcontactcharacteristics(良好的導(dǎo)體)?TiNdoesnot,butcanbeusedforlocalwiring(導(dǎo)電材料，短短程互連布線線)TiSi2TiN27?Photolithography?Mask#11patternalignmentandUVexposure?Rinseawaynon-patternPR?TiNetch?NH4OH:H2O2:H2O(1:1:5)?StripPhotoresistLocalTiNInterconnectThermalTreatinAr減小電阻?1min@800°C28用TiN作為局部互連連引線?ConformallayerofSiO2isdepositedbyCVDorLPCVD(typically1μm)?PSG(磷硅玻璃)orBPSG(硼磷硅玻璃)?磷：Surfacepassivation(表面鈍化)?硼：Glassreflowforpartialplanarization(加熱，令表表面平整)?ChemicalMechanicalPolishing(CMP化學(xué)機(jī)械拋拋光)?Planarizethewafersurface平坦化?PolishwithhighpHsilicaslurry(硅酸鹽研磨磨漿料)ConformalCoatandPlanarize2.8多層金屬互互連的形成成SiO229表面不平坦坦帶來很多多問題,兩種解決方方法：?Photolithography?Mask#12patternalignmentandUVexposure?Rinseawaynon-patternPR?SiO2plasmaetch?Anisotropicetch?StripPhotoresistViasto1stMetal30?選擇第一層層金屬布線線需要與下下層器件結(jié)結(jié)構(gòu)形成連連接的接觸觸孔位置?接觸孔形成成ViaDeposition–TungstenPlugs(插頭)?TiNorTi/TiNbarrierlayer粘結(jié)層/阻擋層，增增強(qiáng)金屬與與SiO2的粘附性?SputteringorCVD(fewtensofnm)?CVDTungsten(W)?ChemicalMechanicalPolishing(CMP)?Planarizethewafersurface?PolishwithhighpHsilicaslurry31?EtchContactHoles(接觸孔的蝕蝕刻)orLineTrenches(溝道)?Filletchedregions(蝕刻區(qū)的填填充)?Planarize(平坦化)–CMPprocess–Alsoremovesmaterialthat“overflowedholesortrenches”DamasceneProcess大馬士革鑲嵌嵌工藝32大馬士革鑲嵌嵌工藝包括：：?StripPhotoresistMetal#1Deposition第一層金屬布布線Photolithography?Mask#13patternalignmentandUVexposure?Rinseawaynon-patternPR?Anisotropicplasmaetch33SiO2Al光刻膠?SputteredAluminum?AlwithsmallamountsofSiandCu-Cureduceselectromigration避免電電遷移移現(xiàn)象象帶來來的斷斷路-Si降低低接接觸觸電電阻阻MultipleMetalLayers?DepositsOxideLayer?CMP?PhotolithographyMask#14?EtchVias?Depositviamaterial?CMP?DepositNextMetalLayer?PhotolithographyMask#15?FinalpassivationlayerofSi3N4isdepositedbyPECVDandpatternedwithMask#16.防止止Na+、K+污染染和和封封裝裝中中的的機(jī)機(jī)械械損損傷傷?Finalannealandalloyinforminggas(10%H2inN2)?30min@400-450°°C?形成成良良好好的的歐歐姆姆接接觸觸，，降降低低Si/SiO2界面面的的電電荷荷34SiO2WTiNSi3N4或SiO2Intelμprocessorchip52MBSRAMchipsona12”wafer?Photosofstate-of-the-artCMOSchips(fromIntelwebsite).?90nmtechnology.35SummaryofKeyideas?ThischapterservesasanintroductiontoCMOStechnology.?Itprovidesaperspectiveonhowindividualtechnologieslikeoxidationandionimplantationareactuallyused.?TherearemanyvariationsonCMOSprocessflowsusedinindustry.?Theprocessdescribedhereisintendedtoberepresentative,althoughitissimplifiedcomparedtomanycurrentprocessflows.Perhapsthemostimportantpointisthatwhileindividualprocessstepslikeoxidationandionimplantationareusuallystudiedasisolatedtechnologies,theiractualuseiscomplicatedbythefactthatICmanufacturingconsistsofmanysequentialsteps,eachofwhichmustintegratetogethertomakethewholeprocessflowworkinmanufacturing.36作業(yè)：MEMS器件制備備最早的MEMS執(zhí)行器之之一：靜靜電驅(qū)動動的微馬馬達(dá)379、靜夜四無鄰鄰，荒居舊業(yè)業(yè)貧。。12月-2212月-22Wednesday,December7,202210、雨中黃葉樹樹，燈下白頭頭人。。21:50:5221:50:5221:5012/7/20229:50:52PM11、以我獨(dú)沈沈久，愧君君相見頻。。。12月-2221:50:5221:50Dec-2207-Dec-2212、故故人人江江海海別別，，幾幾度度隔隔山山川川。。。。21:50:5221:50:5221:50Wednesday,December7,202213、乍見翻翻疑夢，，相悲各各問年。。。12月-2212月-2221:50:5221:50:52December7,202214、他鄉(xiāng)生白白發(fā)，舊國國見青山。。。07十二二月20229:50:52下下午21:50:5212月-2215、比不了得就就不比，得不不到的就不要要。。。十二月229:50下下午12月-2221:50December7,202216、行動出成果果，工作出財(cái)財(cái)富。。2022/12/721:50:5221:50:5207December202217、做做前前，，能能夠夠環(huán)環(huán)視視四四周周；；做做時(shí)時(shí)，，你你只只能能或或者者最最好好沿沿著著以以腳腳為為起起點(diǎn)點(diǎn)的的射射線線向向前前。。。。9:50:52下下午午9:50下下午午21:50:5212月月-229、沒有失敗敗，只有暫暫時(shí)停止成成功！。12月-2212月-22Wednesday,December7,202210、很很多多事事情情努努力力了了未未必必有有結(jié)結(jié)果果，，但但是是不不努努力力卻卻什什么么改改變變也也沒沒有有。。。。21:50:5221:50:5221:5012/7/20229:50:52PM11、成功功就是是日復(fù)復(fù)一日日那一一點(diǎn)點(diǎn)點(diǎn)小小小努力力的積積累。。。12月月-2221:50:5221:50Dec-2207-Dec-2212、世間成事，，不求其絕對對圓滿，留一一份不足，可可得無限完美美。。21:50:5221:50:5221:50Wednesday,December7,202213、不知香積積寺，數(shù)里里入云峰。。。12月-2212月-2221:50:5221:50:52December7,