第1章-緒論英文姜老師

計算機組成原理軟件學(xué)院毛克明了解并掌握計算機硬件的基本知識；在此基礎(chǔ)上著重講述計算機中“數(shù)”的運算存儲計算機(CPU)的設(shè)計和工作原理以及輸入輸出系統(tǒng)。課程目的和安排主要教學(xué)目標(biāo)：在軟件（包括系統(tǒng)軟件和應(yīng)用軟件）設(shè)計過程中必須要了解到的計算機系統(tǒng)的組成與結(jié)構(gòu)。通過本課程學(xué)習(xí)，能夠比較全面地掌握計算機系統(tǒng)的基本概念、基本原理、基本結(jié)構(gòu)和基本分析方法，并建立起計算機系統(tǒng)的完整概念。學(xué)會計算機系統(tǒng)各個主要組成部分的基本原理，常用的性能評價方法，分析方法、計算方法等。課程目的和安排內(nèi)容安排:課堂授課32學(xué)時實驗8學(xué)時緒論（2學(xué)時）計算機中的信息表示（4學(xué)時）組合線路的邏輯設(shè)計（2學(xué)時）時序線路的邏輯設(shè)計（2學(xué)時）算術(shù)邏輯單元（2學(xué)時）復(fù)雜算術(shù)操作（4學(xué)時）指令系統(tǒng)結(jié)構(gòu)（2學(xué)時）中央處理器（2學(xué)時）控制器（4學(xué)時）存儲器（6學(xué)時）輸入輸出（2學(xué)時）考核方式及成績評定總分100分三部分組成平時成績：20%（出勤率，作業(yè)）實驗成績：10%（共兩次實驗）期末試卷成績：70%期末考試方式：閉卷教材及參考書教材：LanJin,BoHatfield.ComputerOrganizationPrinciples,Analysis,andDesign清華大學(xué)出版社參考書：《計算機組成原理》白中英第四版《計算機組成與結(jié)構(gòu)》王愛英清華大學(xué)《計算機系統(tǒng)結(jié)構(gòu)：一種定量的方法》JohnL.Hennessy,David,A.Patterson著ComputerOrganizationChapter1IntroductionChapter1Introduction1.1TheScopeofComputerArchitectureandOrganization1.2ModelingComputerOrganization1.3AHistoricalSketchofComputerEvolution1.4RepresentativeComputerFamilies1.5PerspectivesoftheComputerEvolution1.6Summary1.1TheScopeofComputerA&OMulti-layeredstructureofacomputersystemApplicationSoftwareUserinterfacesSystemSoftwareSysteminterfacesOSDataabstract：servicesusersthroughsystemlibraries;Resourceabstract：supervisehardwarethroughsystemcall;SoftwareHardwareHardwareSystemC,M,C,I,O,CommI/O

Comm.Inter.HardwareDeviceInstructionsetarchitecture;Computerorganization;ImplementationFig1.1Multi-layeredstructureofacomputersystemI,O,Comm.Exceptionhandlingmechanism1.1TheScopeofComputerA&OHardwaresystemLayerInstructionsetarchitectureInstructionsetdesignComputerorganizationfunctionunitsandtheirinterrelationshipControlunitforinstructionsetimplementationinstructionsetimplementationlogicallyImplementationDesignlogicalcircuitandfunctionbyIntegratedcircuitandotherhardwarePhysicallyimplementation1.2ModelingComputerOrganizationThelayeredstructureofcomputerdesignprocessInstructionSetArchitectureLevelInstructionsetdesignLogicalSystemDesignLevelDatapathDesignControlSequenceDesignLevelControlunitdesignDigitalLogicalDesignLevelImplementationofsystemdesignFig1.2Themulti-layeredstructureofthecomputerdesignprocess1.2ModelingComputerOrganizationTheRTLModelofComputerOrganization （Register-TransferLevel）Graphicalform：usediagramstodescribethelogicstructuresofthedatapathTextualform：useaRTLlanguagetodescribethecontrolprocess1.2ModelingComputerOrganizationRTLmodelofacentralprocessingunitControlSectionIRPCMARMBRALUMemorybusGPRTempCPUregistersControlregistersMemoryregistersexample1.2ModelingComputerOrganizationIR:InstructorRegister指令寄存器ALU:ArithmeticLogicUnit算術(shù)邏輯單元GPR:General-PurposeRegister通用寄存器Temp:存儲器PC:ProgramCounter程序計數(shù)器MAR:MemoryAddressRegister記憶體地址寄存器MBR:MemoryBufferRegister記憶體緩沖暫存器1.2ModelingComputerOrganizationControlsequenceofinstructionfetchSendtheaddressoftheinstructiontobefetchedfromtheprogramcounter(PC)tothememoryaddressregister(MAR)Asserta“readmemory”commandtothememorymoduleandwaituntiltheinstructionisavailableinthememorybufferregister（MBR）ThecontentofthePCisincrementedby1sothatitwillpointtotheaddressofthenextinstructionLoadthenewinstructionfromthememorybufferregister（MBR）totheinstructionregister（IR）Deasertthe“readmemory”commandexample1.2ModelingComputerOrganizationInstructionfetch,writteninRTLlanguage:MARPC；memory_read1PCPC

+1Waituntilready=1IRMBRmemory_read0example1.2ModelingComputerOrganizationWeassumethecontrolcyclesforaninstructionfetcharesynchronizedwiththecentralclock,sothewaitcommandintheabovesequenceisomittedMAR（PC）；ReadM

；impliesReadM1

；effectiveonlyinonecycle,soReadM0isunnecessaryPC（PC）+1IRMBRexample1.2ModelingComputerOrganizationTheperformancemodelofacomputersystemMultilayeredstructure.Evaluatetheperformanceofthesystemiscomplex.performanceofhardwarefixedparameterseasytotestperformanceofprogramtestforstandardprogramhowtochoosetestedprogram1.2ModelingComputerOrganizationTheperformancemodelofacomputersystemtwoperformancemeasuresMIPSorMFLOPS（每秒百萬條指令或每秒百萬次浮點操作）T（CPUexecutiontime）：quantifytheeffectivespeedofthecombinedhardware/softwaresystem. MIPS=f(MHz)/CPIave T(sec)=IC×CPIave/f(Hz)AssumethatweknowtheaveragenumberofcyclesperinstructionCPIavewherefistheclockfrequencyandICistheinstructioncount,i.e.,thetotalnumberofinstructionsintherunningprogram1.2ModelingComputerOrganizationCalculationoftheoriginalperformanceofacomputerSupposeacomputerwithaclockfrequencyof100MHzasfourtypesofinstructions,andthefrequencyofusageandtheCPIforeachofthemaregivenintable.FindtheMIPSofthecomputerandtheCPUtimerequiredtorunaprogramof107instructions.ex1.11.2ModelingComputerOrganizationFindtheaverageCPIave:CPIave=0.4*2+0.3*4+0.08*2.5+0.22*3 =0.8+1.2+0.2+0.66=2.86MIPS=100/2.86=35T=107*2.86/(100*106)

=0.286s

MIPS=f(MHz)/CPIaveT(sec)=IC×CPIave/f(Hz)ex1.11.2ModelingComputerOrganizationCalculationoftheupdatedperformanceofacomputerCombiningcomparingandbranchinstructionstogethersothatcompareinstructionscanbereplacedandremoved.Supposeeachcompareinstructionwasoriginallyusedwithonebranchinstruction,andnoweachbranchinstructionischangedtoacompare&branchinstruction.Alsosupposethatthenewproposalwoulddecreasetheclockfrequencyby5%,becausethenowcompare&branchinstructionneedsmoretimetoexecute.FindthenewCPIave,MIPS,andT.CPIave=(0.4*2+0.3*4+0.08*2.5+0.22*3)/0.92 =2.66/0.92=2.9MIPS=(100*95%)/2.9=32.76T=(0.92*107)

*2.9/(0.95*100*106)

=0.28sex1.21.2ModelingComputerOrganizationComparingtheresultsofEX1.1andEx1.2,weseethatthenewproposallowerstheMIPSrate,butdecreasestheexecutiontimeoftheprogram.Thenewproposalisasoftwaremeansthatimprovesthesoftwarecode,butworsensthehardware.Onlytheprogramexecutiontimereflectsthetrueperformanceofthecomputer.Theperformancemodelcanbeappliedtosuperscalar（超標(biāo)量）andpipelined（流水線）processorsaswell.Speedup（加速比）canbeusedtodescribetheirperformances.Sk=kd （kinstructionpipelines,eachwithdepthd）1.3AHistoricalSketchofComputerEvolutionThefirstGeneration:1946-1957，VacuumTubes（真空管）ThesecondGeneration:1958-1964，Transistors

（晶體管）ThethirdGeneration:1965-1971Smallscaleintegration，Upto100devicesonachipMediumscaleintegration，100-3,000devicesonachipThefourthGeneration:1972-1977Largescaleintegration（LSI），3,000-100,000devicesonachipThefifthGeneration:1978todateVerylargescaleintegration（VLSI），100,000-100,000,000devicesonachipUltralargescaleintegration，Over100,000,000devicesonachip1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC(EckertandMauchly?？颂?4,莫奇利36

)EDVAC(vonNeumann)IAS (PrincetonInstituteforAdvancedStudies

)UNIVAC(CommercialComputers)1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC(EckertandMauchly?？颂?4,莫奇利36

)VacuumTubesENIAC-photo1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC：

backgroundElectronicNumericalIntegratorAndComputer（電子數(shù)字積分器和計算器）EckertandMauchly(?？颂?4,莫奇利36)UniversityofPennsylvania（賓夕法尼亞大學(xué)）Trajectorytablesforweapons

(計算新武器的射程及彈道表）Started1943,Finished1946ToolateforwareffortUseduntil19551.3AHistoricalSketchofComputerEvolutionTheFirstGenerationENIAC：

detailsDecimal(notbinary)20accumulators(累加器)of10digitsProgrammedmanuallybyswitches&cables18,000vacuumtubes30tons15,000squarefeet140kWpowerconsumption5,000additionspersecond1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationEDVACElectronicDiscreteVariableComputer（電子離散變量計算機）1945vonNeumannTuring1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationvonNeumann/Turing

StoredProgramconcept(1945)Programcouldberepresentedinaformsuitableforstoringinmemory,andaprogramcouldbesetoralteredbysettingthevaluesofaportionofmemory1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationStructureofvonNuemannmachineMainMemoryArithmeticandLogicUnitProgramControlUnitInputOutputEquipment1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIASComputer

：

(1946)PrincetonInstituteforAdvancedStudies（普林斯頓高級研究院）Completed1952Prototypeofallsubsequentgeneral-purposecomputers（后來通用計算機的原型）1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIAS：details1000x40bitwords(memory)(1000個存儲單元)Binarynumber（數(shù)據(jù)和指令都以2進制存儲）2x20bitinstructions（一個字包含2個指令）NumberWord1+39InstructionWordOpcode8Address12Opcode操作碼Address符號數(shù)值1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationIAS：detailsSetofregisters(storageinCPU)MemoryBufferRegister(MBR)

存儲緩沖寄存器MemoryAddressRegister(MAR)

存儲地址寄存器InstructionRegister(IR)

指令寄存器InstructionBufferRegister(IBR)

指令緩沖寄存器ProgramCounter(PC)

程序計數(shù)器Accumulator(AC)

累加器MultiplierQuotient(MQ)

乘商寄存器StructureofIAS–

detailALUACControlunitdecoderIRPCARCLAInstructionflow1CPUcycle1234DR562CPUcycle789ALUACControlunitdecoderIRPCARDRADDInstructionflow2CPUCycle1234453CPUcycleALUACcontroldecoderIRPCARDRSTAinstructionflow2CPUcycle231453CPUcycleALUACcontroldecoderIRPCARDRNOP指令流程第1個CPU周期第2個CPU周期JMPInstructionflow1CPUcycle2CPUcycle1.3AHistoricalSketchofComputerEvolutionTheFirstGenerationTuringMachine1.3AHistoricalSketchofComputerEvolutionCommercialComputers

：

Eckert-Mauchly

1947-ComputerCorporationUNIVACI(UniversalAutomaticComputer)（通用自動化計算機）USBureauofCensus1950calculations（美國統(tǒng)計局委托制造用于1950年的計算）BecamepartofSperry-RandCorporationLate1950s-UNIVACIIFasterMorememory1.3AHistoricalSketchofComputerEvolutionCommercialComputers

：IBMPunched-cardprocessingequipment1953-the701IBM’sfirststoredprogramcomputerScientificcalculations1955-the702BusinessapplicationsLeadto700/7000series1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationTransistors（晶體管）1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationReplacedvacuumtubesSmallerCheaperLessheatdissipationSolidStatedevice（固態(tài)器件）MadefromSilicon(Sand)（由硅片制成）Invented1947atBellLabsWilliamShockleyetal.1.3AHistoricalSketchofComputerEvolutionTheSecondGenerationSecondgenerationmachinesNCR&RCAproducedsmalltransistormachinesIBM7000DEC-1957ProducedPDP-11.3AHistoricalSketchofComputerEvolutionTheSecondGenerationSecondgenerationmachines1.3AHistoricalSketchofComputerEvolutionTheThirdGeneration

Microelectronics

（微電子學(xué)）Literally-“smallelectronics”Acomputerismadeupofgates,memorycellsandinterconnectionsThesecanbemanufacturedonasemiconductor（半導(dǎo)體）e.g.siliconwafer（硅晶片）1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）IncreaseddensityofcomponentsonchipGordonMoore-cofounderofIntelNumberoftransistorsonachipwilldoubleeveryyear（芯片上的晶體管數(shù)量每年翻一翻）1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）

GrowthinCPUTransistorCount

1.3AHistoricalSketchofComputerEvolutionMoore’sLaw

（1965）Since1970’sdevelopmenthasslowedalittleNumberoftransistorsdoublesevery18monthsCostofachiphasremainedalmostunchangedHigherpackingdensitymeansshorterelectricalpaths,givinghigherperformanceSmallersizegivesincreasedflexibilityReducedpowerandcoolingrequirementsFewerinterconnectionsincreasesreliability1.3AHistoricalSketchofComputerEvolutionIBM360series1964Replaced(¬compatiblewith)7000seriesFirstplanned“family”ofcomputersSimilaroridenticalinstructionsetsSimilaroridenticalO/SIncreasingspeedIncreasingnumberofI/Oports(i.e.moreterminals)IncreasedmemorysizeIncreasedcostMultiplexedswitchstructure1.3AHistoricalSketchofComputerEvolutionDECPDP-8

1964Firstminicomputer(afterminiskirt!)DidnotneedairconditionedroomSmallenoughtositonalabbenchEmbeddedapplications&OEMBUSSTRUCTURE1.3AHistoricalSketchofComputerEvolutionDECPDP-8

：BusStructureOMNIBUSConsoleControllerCPUMainMemoryI/OModuleI/OModule1.3AHistoricalSketchofComputerEvolutionSemiconductorMemory1970Fairchild(仙童)Sizeofasinglecorei.e.1bitofmagneticcorestorageHolds256bitsNon-destructivereadMuchfasterthancoreCapacityapproximatelydoubleseachyear1.3AHistoricalSketchofComputerEvolutionMicroprocessors

（微處理器）：40041971FirstmicroprocessorAllCPUcomponentsonasinglechip4bit1.3AHistoricalSketchofComputerEvolutionMicroprocessors

（微處理器）：4004Firstmicroprocessorin1971:Intel4004108kHz,0.06MIPS2300transistors

(10microns)Buswidth:4bitsMemory:640bytes1.3Evolution(計算機發(fā)展)

TheFourthGenerationTheFourthGeneration

Followedin1972by80088bitBothdesignedforspecificapplications1974-8080Intel’sfirstgeneralpurposemicroprocessor1.3Evolution(計算機發(fā)展)

TheFourthGenerationMicrocomputer:

AppleII1977

SteveJobs,SteveWozniak1.3Evolution(計算機發(fā)展)

TheFourthGenerationMicrocomputer:IBMPC1981

Intel8088,4.77MHz1.3Evolution(計算機發(fā)展)

TheFourthGenerationMicrocomputer:IBMPCOthers1.3Evolution(計算機發(fā)展)

TheFourthGenerationSpeedingitupPipelining

(流水線)OnboardcacheOnboardL1&L2cacheBranchpredictionDataflowanalysisSpeculativeexecution(預(yù)測執(zhí)行)1.4RepresentativeComputerFamiliesPentiumSPARCPowerPC1.4RepresentativeComputerFamiliesPentium4004(1971,4bits,0.108MHz,2300transistorsonachip,640Bmemory)8008(1972,8bits,0.108MHz,3500transistorsonachip,16KBmemory)8080(1974,8bits,2MHz,6000transistorsonachip,64KBmemory)8086(1978,16bits,5~10MHz,29000transistorsonachip,1MBmemory)8088(1979,aslowerandcheaperversionof8086,withsameparameters)80286(1982,16bits,8~12MHz,134000transistorsonachip,16MBmemory)80386(1985,32bits,16~33MHz,275000transistorsonachip,4GBmemory)80486(1989,32bit,25~100MHz,1.2Mtransistors)1.4RepresentativeComputerFamiliesPentiumPentium(1993,32bitsdatapath,64-bitbus,60~233MHz,3.1Mtransistors,2-issuesuperscalarofpipelinedepth=5)Pentiumpro(1995,64bitsdatapath,64-bitbus,150~200MHz,5.5Mtransistors,2-issuesuperscalarofpipelinedepth=12)PentiumⅡ

(1997,32bits,230~400MHz,7.5Mtransistors,PentiumⅡplusMMXinstructions)PentiumⅢ

(1999,64bit1-Gbpssystembus,500~1000MHz,95Mtransistors,SSEinstructions,superscalarprocessorpipelinedepth=10)PentiumⅣ

(2000,64bit32-Gbpssystembus,1.3~1.8GHz,42Mtransistors,MMXandSSEinstructions,superscalarpipelinedepth>=20)ItaniumⅣ(IA-64architecture,6-wide10-stagedeeppipeline)安騰1.4RepresentativeComputerFamiliesSPARCFamilyOriginatedfromSunMicrosystemsCorporationin1987.（工作站）Designedtobemorepowerfulthanordinarypersonalcomputers.Aimingathigh-endapplicationsSUN-1,SUN-2,SUN-31987ScalableProcessorARChitecure(可伸縮體系結(jié)構(gòu))32-bits,36MHzRISCmachine1995UltraSPARC，64-bitsmachinewith23newinstructionscalledtheVIS(可視信號系統(tǒng)).1.4RepresentativeComputerFamiliesUltraSPARCUltraSPARC-Ⅰ：0.5umCMOS,167MHzUltraSPARC-Ⅱ：0.25um,250~480MHz，apipelineof9stages.UltraSPARC-Ⅲ：0.18um,750~900MHz，apipelineof14stages，4integerexecutionunitsandthreefloating-pointunits,offeringsuper-scalarperformance（超標(biāo)量性能）.1.4RepresentativeComputerFamiliesPowerPCFamily1990’s,manufacturedbyIBM,MotorolaandAppleFirstusedinIBMRISCSystemRS/6000PowerPC601：1993，32-bitprocessor,50~100MHz，2.8Mtransistors，3independentexecutionunits（integer,floating-point,andbranchprocessing）,for3-issuesuperscalaroperationwithpipelinedepthsequalto4forintegerinstructionsand6forfloating-pointinstruction.PowerPC603：1994，32-bitprocessor，100~300MHz，1.6~2.6Mtransistors，5independentexecutionunits,lowpowerdesign.PowerPC604：1994，32-bitprocessor，166~350MHz，3.6M~5.1Mtransistors，6independentexecutionunits，3integerunits,afloating-pointunit,amemoryload/storeunit,andabranchprocessingunit-for4-issuesuperscalaroperation1.4RepresentativeComputerFamiliesPowerPCFamilyPowerPC620：64-bitprocessor,superscalararchitecturelikethePowerPC604，outoforderexecutionofinstructionsanddynamicbranchprediction,targetedforhigh-endsystems.MPC740/750(G3)：1997，64-bitprocessor，200~366MHz，6.35Mtransistors，integrating2*32KBlevel-1cacheand256KB~1MBlevel-2cacheinthemainprocessorchip.MPC7450(G4)：1999，64-bitprocessor，733MHz，11executionunits-aload/storeunit,abranchunit,4integerunits,afloating-pointunit,and4vectoredoperationunits-for4-issuesuperscalaroperatingwithpipelinedepthequalto7.1.5PerspectivesoftheComputerEvolut