數(shù)字邏輯第六章5

Chapter6

CombinationalLogicDesignPractices

(組合邏輯設(shè)計(jì)實(shí)踐)DocumentationStandardandCircuitTiming(文檔標(biāo)準(zhǔn)和電路定時(shí))CommonlyUsedMSICombinationalLogicDevice(常用的中規(guī)模組合邏輯器件)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)1Decoder(譯碼器)CascadingBinaryDecoders(譯碼器的級聯(lián))RealizeaLogicCircuitbyUsingDecoder

(利用譯碼器實(shí)現(xiàn)邏輯電路)ReviewofLastClass(內(nèi)容回顧)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)2N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L用74x138設(shè)計(jì)4-16譯碼器思路：16個(gè)輸出需要

片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2任何時(shí)刻只有一片在工作。4個(gè)輸入中，哪些位控制片選哪些位控制輸入CascadingBinaryDecoders

(級聯(lián)二進(jìn)制譯碼器）3Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138設(shè)計(jì)5-32譯碼器)Howmany74x138chipstobeusedwith32outputs?(32個(gè)輸出需要多少片74x138？)Controlthatonlyonechipworksinanytime(控制任何時(shí)刻只有一片工作)——UsetheEnableInputs(利用使能端)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)4Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138設(shè)計(jì)5-32譯碼器)Controlinputsofthreelow-orderbitsofa5-bitcodeword(5個(gè)輸入的低3位控制輸入)Controlchipsoftwohigh-orderbitsofa5-bitcodeword

(5個(gè)輸入的高2位控制片選)——Use2-to-4Decoder(利用2-4譯碼器)圖6－37DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)5用譯碼器和邏輯門實(shí)現(xiàn)邏輯函數(shù)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)當(dāng)使能端有效時(shí)Yi=miDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)6用譯碼器和邏輯門實(shí)現(xiàn)邏輯函數(shù)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)7Decoder(譯碼器)Encoder

(編碼器)(優(yōu)先編碼器的級聯(lián)和應(yīng)用)ReviewofLastClass(內(nèi)容回顧)CascadingPriorityEncodersDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)8A2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2個(gè)74x148級聯(lián)為16－4優(yōu)先編碼器9輸入：由864，需8片74x148每片優(yōu)先級不同（怎樣實(shí)現(xiàn)？）保證高位無輸入時(shí)，次高位才工作——高位芯片的EO端接次高位芯片的EI端用8-3優(yōu)先編碼器74x148級聯(lián)為64-6優(yōu)先編碼器A2A1A0GSEOEII7I0片間優(yōu)先級的編碼——利用第9片74x148

每片的GS端接到第9片的輸入端

第9片的輸出作為高3位（RA5～RA3）片內(nèi)優(yōu)先級片間優(yōu)先級輸出：6位低3位高3位8片輸出A2～A0通過或門作為最終輸出的低3位RA2～RA0DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)10Decoders

(譯碼器)Encoders

(編碼器)Three-StateDevices

(三態(tài)器件)Multiplexer(多路復(fù)用器)標(biāo)準(zhǔn)MSI多路復(fù)用器74x151、74x153、74x157

擴(kuò)展多路復(fù)用器利用多路復(fù)用器實(shí)現(xiàn)邏輯函數(shù)多路分配器(Demultiplexer)——利用帶使能端的譯碼器使能端作為數(shù)據(jù)輸入端ReviewofLastClass(內(nèi)容回顧)11當(dāng)使能端有效時(shí)，最小項(xiàng)之和形式ENABCD0D1D2D3D4D5D6D7YY74x151實(shí)現(xiàn)邏輯函數(shù)F=(A,B,C)(0,1,3,7)CBAVCCF用多路復(fù)用器設(shè)計(jì)組合邏輯電路DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)12思考：利用74x151實(shí)現(xiàn)邏輯函數(shù)F=(W,X,Y,Z)(0,1,3,7,9,13,14)降維：由4維3維Shannon’sexpansiontheorems

(香農(nóng)展開定理)1、F(1,X2,X3,…,Xn)=F(0,X2,X3,…,Xn)=0,填02、F(1,X2,X3,…,Xn)=F(0,X2,X3,…,Xn)=1，填13、F(1,X2,X3,…,Xn)=1，F(xiàn)(0,X2,X3,…,Xn)=0，填X14、F(1,X2,X3,…,Xn)=0，F(xiàn)(0,X2,X3,…,Xn)=1，填X1’DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)13YZWX00

01

11

10000111101111111YWX000111100110ZZZZZ’0思考：利用74x151實(shí)現(xiàn)邏輯函數(shù)F=(W,X,Y,Z)(0,1,3,7,9,13,14)降維：由4維3維DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)14ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZ利用74x151實(shí)現(xiàn)F=(W,X,Y,Z)(0,1,3,7,9,13,14)0

2

6

41

3

7

5YWX000111100110ZZZZZ’0DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)15Abinarydecoderwithanenableinputcanbeusedasademultiplexer(利用帶使能端的二進(jìn)制譯碼器作為多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_L數(shù)據(jù)輸入SRCEN_L利用74x139實(shí)現(xiàn)2位4輸出多路分配器（Figure6-65）DSTSEL0DSTSEL1DSTSEL2地址選擇——Enableinputisconnectedtothedataline

(利用使能端作為數(shù)據(jù)輸入端)數(shù)據(jù)輸入SRCEN_L16譯碼器編碼器三態(tài)器件多路復(fù)用器ParityCircuit

(奇偶校驗(yàn)器)Comparator

(比較器)奇校驗(yàn)：輸入有奇數(shù)個(gè)1，輸出為1偶校驗(yàn)：輸入有偶數(shù)個(gè)1，輸出為1利用異或運(yùn)算實(shí)現(xiàn)9位奇偶發(fā)生器74x280

奇偶校驗(yàn)的應(yīng)用——檢測代碼在傳輸和存儲過程中是否出現(xiàn)差錯(cuò)。ReviewofLastClass(內(nèi)容回顧)179-bitOdd/EvenParityGenerator74x280(9位奇偶校驗(yàn)發(fā)生器74x280（P291圖5－75）ABCDEFGHIEVENODD74x280DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)18Parity-CheckingApplications

(奇偶校驗(yàn)的應(yīng)用)用于檢測代碼在傳輸和存儲過程中是否出現(xiàn)差錯(cuò)AEVENODD74x280HIAEVENODD74x280HI發(fā)端收端DB[0:7]DB[0:7]ERROR發(fā)端保證有偶數(shù)個(gè)1收端ODD有效表示出錯(cuò)奇數(shù)EVEN196.9Comparator（比較器）ComparetwoBinarywordsandindicatewhethertheyareequal(比較2個(gè)二進(jìn)制數(shù)值并指示其是否相等的電路)Comparator:CheckiftwoBinarywordsareequal

(等值比較器：檢驗(yàn)數(shù)值是否相等)MagnitudeComparator:Comparetheirmagnitude(Greaterthan,Equal,Lessthan)(數(shù)值比較器：比較數(shù)值的大?。?gt;,=,<）)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)206.9Comparator（比較器）Howtobuilda1-bitComparator?

(如何構(gòu)造1位等值比較器？？)——UseXOR(XNOR)

(利用異或門（同或門）)ABDIFFABEQDIFF:differentEQ:equalDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)21DIFFA0B0A1B1A2B2A3B3給出足夠的異或門和寬度足夠的或門，可以搭建任意輸入位數(shù)的等值比較器。HowtoBuildaN-bitComparator?

(如何構(gòu)造多位等值比較器？？)必須每位都相等——并行比較——串行比較4位等值比較器DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)22AnIterativeComparator

(迭代比較電路)XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQO——每位串行比較ABEQEQOEQI迭代的方法可能節(jié)省費(fèi)用，但速度慢用于級聯(lián)的輸入DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)Figure6-7723EQ_LABLT_LGT_L1-BitMagnitudeComparator

(一位數(shù)值比較器)①A>B（A=1,B=0）則A·B’=1可作為輸出信號②A<B（A=0,B=1）則A’·B=1可作為輸出信號③A=B，則A⊙B=1，可作為輸出信號輸出低電平有效EQ_L=A·B’+A’·B=AB=(A⊙B)’LT:LessThanEQ:EqualGT:GreaterThan(A’·B)’(A·B’)’DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)24n-BitMagnitudeComparator

(多位數(shù)值比較器)A(A3A2A1A0)

和

B(B3B2B1B0)自高而低逐位比較EQ=(A3⊙B3)·(A2⊙B2)·(A1⊙B1)·(A0⊙B0)GT=(A3>B3)LT=EQ’·GT’=(EQ+GT)’或(A3=

B3)·(A2=

B2)·

(A1>B1)或(A3=

B3)·(A2=

B2)·(A1=

B1)·

(A0>B0)或(A3=

B3)·

(A2>B2)A3·

B3’A2·

B2’A1·

B1’A0·

B0’⊙⊙⊙⊙⊙⊙+++DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)2574x854-BitComparator74x85

(4位比較器74x85)A0A1A2A3ALTBINAEQBINAGTBIN級聯(lián)輸入，用于擴(kuò)展ALTBOUT=(A<B)+(A=B)·ALTBIN通常低位的輸出接高位的輸入A=B：低位和高位都相等A高位>B高位A高位=B高位&A低位>B低位A>BAEQBOUT=(A=B)·AEQBINAGTBOUT=(A>B)+(A=B)·AGTBINDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)26SerialExpandingComparators

(比較器的串行擴(kuò)展)XD[11:0]YD[11:0][3:0][7:4][11:8]X<YX=YX>Y+5VA<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x853片74x85構(gòu)成12位比較器低位高位DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)27P0P1P2P3P4P5P6P78位比較器74x682內(nèi)部邏輯圖：圖6-82問題1：怎樣表示以下輸出？高電平有效：PDIFFQ高電平有效：PEQQ高電平有效：PGEQ高電平有效：PLTQ（圖6-81）GELT問題2：能否擴(kuò)展？？注意：沒有級聯(lián)輸入端DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)283片74x682構(gòu)成24位比較器P0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>Q[7:0][15:8][23:16]P[23:0]Q[23:0]PEQQPGTQParalelExpandingComparators

(比較器的并行擴(kuò)展)296.10Adder(加法器)HalfAdderand

FullAdder（半加器和全加器）0000010110011110ABSCO(半加器真值表)Sum(相加的和):

S=A’·B+A·B’=ABCarry(向高位的進(jìn)位)：CO=A·B0000000101010010111010001101101101011111CIXYSCO(全加器真值表)TruthTableofHalfAdderTruthTableofFullAdderDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)30SCOXYCIS=XYCIX·Y00100111CIXY0001111001COX·CICO=

+

+Y·CI=X·Y+(X+Y)·CI0000000101010010111010001101101101011111CIXYSCO全加器真值表6.10Adder(加法器)6.10.1HalfAddersand

FullAdders（半加器和全加器）TruthTableofFullAdderDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)316.10.2RippleAdders(串行進(jìn)位加法器)(缺點(diǎn)：運(yùn)算速度慢，有較大的傳輸延遲)tADD=tXYCout+(n-2)*tCinCout+tCinSXYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3=0回顧：串行比較器——ImproveSpeed:ParallelAdder

(提高速度：并行加法器)Disadvantage:Slow,MorePropagationDelayDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)32XYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQOAnIterativeComparator(串行比較器)RippleAdder(串行加法器)PrimaryInputs(主輸入)PrimaryOutputs(主輸出)BoundaryInputs(邊界輸入)BoundaryOutputs(邊界輸出)級聯(lián)輸出33AnIterativeCircuit（迭代電路）Iterative：重復(fù)的,反復(fù)的,[數(shù)]迭代的PICICOPOPICICOPOPICICOPOC0C1C2CnPO0PO1POn-1主輸出PI0PI1PIn-1主輸入邊界輸入邊界輸出級聯(lián)輸出DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)346.10.3Subtractors(減法器)

方法一：利用真值表化簡設(shè)計(jì)減法器二進(jìn)制減法表（表2-3）D=XYBI

BO=X’·Y+X’·BI+Y·BI

方法二：利用加法器設(shè)計(jì)減法器（X－Y）相當(dāng)于（X＋Y補(bǔ)）對Y求補(bǔ)：逐位求反＋11XYCICOSXYCICOSXYCICOSB_LX0Y0X1Y1XnYnD0D1DnDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)35一位全加器：S=XYCiCi+1=X·Y+(X+Y)·Ci6.10.4Carry-LockaheadAdders

(先行進(jìn)位加法器)先行進(jìn)位法：第i

位的進(jìn)位輸入信號可以由該位以前的各位狀態(tài)決定。Ci+1=(Xi·Yi)+(Xi+Yi)·

Ci=Gi

+Pi

·Ci進(jìn)位產(chǎn)生信號進(jìn)位傳遞信號0000000101010010111010001101101101011111CiXYSCi+1全加器真值表DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)36先行進(jìn)位法：第i

位的進(jìn)位輸入信號可以由該位以前的各位狀態(tài)決定。C0=0Ci+1=Gi+Pi

·CiC0=0C1=G0+P0·C0C2=G1+P1·C1=G1+P1·(G0+P0·C0)=G1+P1·G0+P1·P0·C0……Cn=Gn+Pn·Cn（圖6-89）展開為“與-或”式：三級延遲MSI加法器74x283圖6-876-88DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)6.10.4Carry-LockaheadAdders

(先行進(jìn)位加法器)376.10.6MSIArithmeticandLogicUnits

(ALU,MSI算術(shù)邏輯單元)Performanyofanumberofdifferentarithmeticandlogicaloperationsonapairofb-bitoperands.(對2個(gè)b位的操作數(shù)進(jìn)行若干不同的算術(shù)和邏輯運(yùn)算)S0~S3MCINA0~A3B0~B3GPF0~F3COUTA=B74x181輸入數(shù)據(jù)輸出數(shù)據(jù)0算術(shù)/1邏輯選擇特定操作Table6-70Figure6-906-916-926-93DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)38S1S0Y00011011A·BA+BABA’功能表設(shè)計(jì)函數(shù)發(fā)生器，其功能表如下：S1S0ABY00000001真值表1、填寫真值表2、選擇器件用基本門電路實(shí)現(xiàn)利用卡諾圖化簡用譯碼器實(shí)現(xiàn)轉(zhuǎn)換為最小項(xiàng)之和用數(shù)據(jù)選擇器實(shí)現(xiàn)3、電路處理注意有效電平DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)39組合邏輯部分小結(jié)第4章組合邏輯設(shè)計(jì)原理第6章組合邏輯設(shè)計(jì)實(shí)踐DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)40第4章基本原理開關(guān)代數(shù)基礎(chǔ)組合邏輯的基本分析、綜合方法冒險(xiǎn)開關(guān)代數(shù)的公理、定理對偶、反演規(guī)則邏輯函數(shù)的表示法

分析步驟，利用公式進(jìn)行化簡

設(shè)計(jì)方法、步驟利用卡諾圖化簡，電路處理無關(guān)項(xiàng)的化簡、多輸出函數(shù)的化簡——冒險(xiǎn)的檢查和消除DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)41組合電路的分析分析的目的：確定給定電路的邏輯功能分析步驟：由輸入到輸出逐級寫出邏輯函數(shù)表達(dá)式對輸出邏輯函數(shù)表達(dá)式進(jìn)行化簡判斷邏輯功能（列真值表或畫波形圖）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)42分析圖示邏輯電路的功能B3B2B1B0G3G2G1G0解：1、寫表達(dá)式2、列真值表3、分析功能0000000100100011010001010110011110001001101010111100110111101111B3B2B1B0G3G2G1G0000000010011G3=B3G2=B3B2G1=B2B1G0=B1B0二進(jìn)制碼至格雷碼的轉(zhuǎn)換電路0010011001110101010011001101111111101010101110011000DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)43組合電路的綜合問題描述邏輯抽象選定器件類型函數(shù)化簡電路處理將函數(shù)式變換電路實(shí)現(xiàn)真值表或函數(shù)式用門電路用MSI組合電路或PLDDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)440000000001010101101010101111111100011011000110110001101100011011X1X0Y1Y00000000000000000000000010010001100000010010001100000001101101001P3P2P1P0設(shè)計(jì)2位數(shù)乘法器1、列真值表輸入：X、Y（2位）輸出：乘積P（4位）P3=X1·X0·Y1·Y0Y1Y0X1X0000111

1000011110P21112、用門電路實(shí)現(xiàn)利用卡諾圖化簡

注意：多輸出函數(shù)3、電路處理45Y1Y0X1X0000111

10000111100111111111111111Y1Y0X1X0000111

10000111101111Y1Y0X1X0000111

1000011110P2111P3=X1·X0·Y1·Y0P2=X1·Y1·(X1·X0·Y1·Y0)’=X1·Y1·P3’46Y1Y0X1X0000111

1000011110P1111111Y1Y0X1X0000111

1000011110P01111P3=X1·X0·Y1·Y0P2=X1·Y1·P3’P1=X1·Y0·P3’+X0·Y1·P3’P0=X0·Y0Y1Y0X1X0000111

1000011110P21111147比較：按多輸出化簡（藍(lán)色）按單個(gè)卡諾圖化簡（黑色）P3=X1·

X0·

Y1·

Y0P2=X1·X0·Y1+X1·Y1·Y0’P1=X1·Y1’·Y0+X1·X0’·Y0+

X0·Y1·Y0’

+X1’·X0·Y1P0=X0·

Y0P3=X1·X0·Y1·Y0P2=X1·Y1·P3’P1=X1·Y0·P3’+X0·Y1·P3’P0=X0·Y0考慮：用譯碼器實(shí)現(xiàn)——直接表示為標(biāo)準(zhǔn)和形式DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)48人的血型有A、B、AB、O四種，輸血者的血型與受血者的血型必須符合下面的關(guān)系。設(shè)計(jì)邏輯電路判斷輸血者與受血者的血型是否符合規(guī)定。ABABOABABO輸血者受血者解：1、邏輯抽象，得真值表

用X1X0對應(yīng)輸血者的血型（00~11）用Y1Y0對應(yīng)受血者的血型（00~11）輸出F，1表示可以輸血，0表示不行000110110001101100

00000100

1000

1101

00X1X0

Y1Y0F101002、用門電路實(shí)現(xiàn)卡諾圖化簡（略）利用譯碼器利用多路復(fù)用器49第6章組合邏輯設(shè)計(jì)實(shí)踐常用的中規(guī)模集成電路（MSI）編碼器、譯碼器、多路復(fù)用器、奇偶校驗(yàn)、比較器、加法器、三態(tài)器件掌握基本功能，級聯(lián)的方法綜合應(yīng)用：利用基本MSI器件作為基本單元設(shè)計(jì)更復(fù)雜的組合邏輯電路文檔標(biāo)準(zhǔn)和電路定時(shí)（了解）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)50設(shè)計(jì)減法器

方法一：利用真值表化簡二進(jìn)制減法表（表2-3）D=XYBI

BO=X’·Y+X’·BI+Y·BI

方法二：利用加法器設(shè)計(jì)減法器（X－Y）相當(dāng)于（X＋Y補(bǔ)）對Y求補(bǔ)：逐位求反＋11XYCICOSXYCICOSXYCICOSB_LX0Y0X1Y1XnYnD0D1DnDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)51設(shè)計(jì)將BCD碼轉(zhuǎn)換成余3碼的碼制轉(zhuǎn)換電路方案一：利用基本門電路（SSI）實(shí)現(xiàn)1、列真值表001101000101011001111000100110101011110000000001001000110100010101100111100010011010……1111X3~X0F3~F0d2、卡諾圖化簡（多輸出函數(shù)）3、電路處理，得到電路圖“與-或”式“與非-與非”式“或-與”式“或非-或非”式方案二：利用中規(guī)模集成電路MSI實(shí)現(xiàn)——譯碼器實(shí)現(xiàn)多輸出函數(shù)思考：有沒有更好的方法？？？DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)52X1X0X3X2000111

1000011110F311111ddddddX1X0X3X2000111

1000011110F211111ddddddX1X0X3X2000111

1000011110F111111ddddddX1X0X3X2000111

1000011110F011111dddddd53設(shè)計(jì)將BCD碼轉(zhuǎn)換成余3碼的碼制轉(zhuǎn)換電路一個(gè)更好的方法：余3碼＝BCD碼＋3——利用加法器（MSI）實(shí)現(xiàn)A0A1A2A3B0B1B2B3C0S0S1S2S3C474x283X0X1X2X3F0F1F2F3VCC1100DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)54實(shí)現(xiàn)兩個(gè)BCD碼的加法運(yùn)算思考：兩個(gè)BCD碼與兩個(gè)4位二進(jìn)制數(shù)相加的區(qū)別如果(X+Y)產(chǎn)生進(jìn)位信號C或在1010~1111之間需要進(jìn)行修正——結(jié)果加6利用F表示是否需要修正F=C+S3·S2·S1·S0+S3·S2·S1·S0’+S3·S2·S1’·S0+S3·S2·S1’·S0’+S3·S2’·S1·S0+S3·S2’·S1·S0’X1X0X3X2000111

1000011110111111F=C+S3·S2+S3·S1DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計(jì)及應(yīng)用)55相加判別修正A0S0A1S1A2S2A3S3B0B1B2B3C0

C474x283A0S0A