at89s51單片機相關(guān)的3000字英文

at89s51單片機相關(guān)的3000字英文篇一：AT89S51單片機外文翻譯

TheDescriptionofAT89S51

1GeneralDescription

TheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandispatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bybiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.

TheAT89S51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.

TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2Ports

Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.

Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternal

pull-ups.

Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.

3SpecialFunctionRegisters

Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable3-1.

0F8H0F0H0E8H0E0H0D8H0D0H0C8H0C0H0B8H0B0H0A8H0A0H98H

90H

88H

0FFH

0F7H

0EFH

0E7H

0DFH

0D7H

0CFH

0C7H

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

80H

87H

Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.

Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybe

usedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.

InterruptRegisters:TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.

DualDataPointerRegisters:Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.

PowerOffFlag:ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1〞duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.

4MemoryOrganization

MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.4.1ProgramMemory

CC,programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.4.2DataMemory

TheAT89S51implements128bytesofon-chipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.5WatchdogTimer(One-timeEnabledwithReset-out)

TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthrough

篇二：AT89s51單片機外文翻譯

畢業(yè)設(shè)計〔論文〕外文翻譯

畢業(yè)設(shè)計〔論文〕題目：基于單片機的點陣LED顯示屏系統(tǒng)的設(shè)計

外文題目：TheDescriptionofAT89S51

譯文題目：AT89S51概述

學生姓名：費禹翔專業(yè)：電氣工程及其自動化0603班指導教師：李翠玉

TheDescriptionofAT89S51

1GeneralDescription

TheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandispatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bybiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.

TheAT89S51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.

TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2Ports

Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.

Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternal

pull-ups.

Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.

3SpecialFunctionRegisters

Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable3-1.

0F8H0F0H0E8H0E0H0D8H0D0H0C8H0C0H0B8H0B0H0A8H0A0H98H

90H

88H

0FFH

0F7H

0EFH

0E7H

0DFH

0D7H

0CFH

0C7H

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

80H

87H

Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.

Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybe

usedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.

InterruptRegisters:TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.

DualDataPointerRegisters:Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.

PowerOffFlag:ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1〞duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.

篇三：AT89S51單片機

AT89S51

AT89S51單片機的硬件組成

單片機內(nèi)硬件組成構(gòu)造如圖2-1所示。

圖2-1AT89S51單片機片內(nèi)構(gòu)造

有如下功能部件和特性：

〔1〕8位微處理器〔CPU〕；

〔2〕數(shù)據(jù)存儲器〔128BRAM〕；

〔3〕程序存儲器〔4KBFlashROM〕；

〔4〕4個8位可編程并行I/O口〔P0口、P1口、P2口和P3口〕；

〔5〕1個全雙工的異步串行口；

〔6〕2個可編程的16位定時器/計數(shù)器；

〔7〕1個看門狗定時器；

〔8〕中斷系統(tǒng)具有5個中斷源、5個中斷向量；

〔9〕特殊功能存放器〔SFR〕26個；

〔10〕低功耗形式有空閑形式和掉電形式，且具有掉電形式下的中斷恢復形式；

〔11〕3個程序加密鎖定位。

與AT89C51相比，AT89S51有更突出的優(yōu)點：

〔1〕增加在線可編程功能ISP〔InSystemProgram〕，字節(jié)和頁編程，現(xiàn)場程序調(diào)試和修改更加方便靈敏；

〔2〕數(shù)據(jù)指針增加到兩個，方便了對片外RAM的訪問過程；

〔3〕增加了看門狗定時器，進步了系統(tǒng)的抗干擾才能；

〔4〕增加斷電標志；

〔5〕增加掉電狀態(tài)下的中斷恢復形式。

單片機內(nèi)各功能部件通過片內(nèi)單一總線連接而成〔見圖2-1〕，根本構(gòu)造照舊是CPU加上外圍芯片的傳統(tǒng)微機構(gòu)造。

CPU對各種功能部件的控制是采用特殊功能存放器〔SFR，SpecialFunctionRegister〕的集中控制方式。單片機內(nèi)部件功能

1〕CPU〔微處理器〕

8位的CPU，與通用CPU根本一樣，同樣包括了運算器和控制器兩大局部，還有面向控制的位處理功能。

2〕數(shù)據(jù)存儲器〔RAM〕

片內(nèi)為128B〔52子系列為256B〕，片外最多可擴64KB。片內(nèi)128B的RAM以高速RAM的形式集成，可加快單片機運行的速度和降低功耗。

3〕程序存儲器〔FlashROM〕

片內(nèi)集成有4KB的Flash存儲器〔AT89S52那么為8KB；AT89C55片內(nèi)20KB〕，如片內(nèi)容量不夠，片外可外擴至64KB。

4〕中斷系統(tǒng)

具有5個中斷源，2級中斷優(yōu)先權(quán)。

5〕定時器/計數(shù)器

2個16位定時器/計數(shù)器〔52子系列有3個〕，4種工作方式。

6〕1個看門狗定時器WDT

當CPU由于干擾使程序陷入死循環(huán)或跑飛時，WDT可使程序恢復正常運行。

7〕串行口

1個全雙工的異步串行口，4種工作方式?？蛇M展串行通信，擴展并行I/O口，還可與多個單片機構(gòu)成多機系統(tǒng)。

8〕P0口、P1口、P2口和P3口

4個8位并行I/O口。

9〕特殊功能存放器〔SFR〕

26個，對片內(nèi)各功能部件管理、控制和監(jiān)視。是各個功能部件的控制存放器和狀態(tài)存放器，映射在片內(nèi)RAM區(qū)80H～FFH內(nèi)。

AT89S51完全兼容AT89C51，在充分保存原來軟、硬件條件下，完全可以用AT89S51直接代換。AT89S51的引腳功能

AT89S51與51系列中各種型號芯片的引腳互相兼容。目前多采用40只引腳雙列直插，如圖2-2所示。引腳按其功能可分為如下3類：

1〕電源及時鐘引腳—VCC、VSS；XTAL1、XTAL2。

2〕控制引腳—、ALE/PROG、/VPP、RST〔RESET〕EAPSEN3〕I/O口引腳——P0、P1、P2、P3，為4個8位I/O口

電源及時鐘引腳

1．電源引腳

1〕VCC〔40腳〕：+5V電源。

2〕VSS〔20腳〕：數(shù)字地。

2．時鐘引腳

1〕XTAL1〔19腳〕：片內(nèi)振蕩器反相放大器和時鐘發(fā)生器電路輸入端。用片內(nèi)振蕩器時，該腳接外部石英晶體和微調(diào)電容。外接時鐘源時，該腳接外部時鐘振蕩器的信號。

2〕XTAL2〔18腳〕：片內(nèi)振蕩器反相放大器的輸出端。當使用片內(nèi)振蕩器，該腳連接外部石英晶體和微調(diào)電容。當使用外部時鐘源時，本腳懸空。

3．控制引腳

1〕RST(RESET，9腳)

復位信號輸入，在引腳加上持續(xù)時間大于2個機器周期的高電平，可使單片機復位。正常工作，此腳電平應(yīng)≤0.5V。

當看門狗定時器溢出輸出時，該腳將輸出長達96個時鐘振蕩周期的高電平。

2〕/VPP(EnableAddress/VoltagePulseofPrograming，31腳)EAEA引腳第一功能：外部程序存儲器訪問允許控制端。

=1：在PC值不超出0FFFH〔即不超出片內(nèi)4KBFlash存儲器的地址范圍〕時，單片機讀片內(nèi)程序存儲器〔4KB〕中的程序，但PC值超出0FFFH〔即超出片內(nèi)4KBFlash地址范圍〕時，將自動轉(zhuǎn)向讀取片外60KB〔1000H-FFFFH〕程序存儲器空間中的程序。EA=0：只讀取外部的程序存儲器中的內(nèi)容，讀取的地址范圍為0000H～FFFFH，片內(nèi)的4KBFlash程序存儲器不起作用。

VPP：引腳第二功能，對片內(nèi)Flash編程，接編程電壓。

3〕ALE/PROGAddressLatchEnable/PROGramming，30腳〕

ALE為CPU訪問外部程序存儲器或外部數(shù)據(jù)存儲器提供地址鎖存信號，將低8位地址鎖存在片外的地址鎖存器中。此外，單片機正常運行時，ALE端一直有正脈沖信號輸出，此頻率為時鐘振蕩器頻率fosc的1/6。可用作外部定時或觸發(fā)信號。

注意，每當AT89S51訪問外部RAM時〔執(zhí)行MOVX類指令〕，要喪失一個ALE脈沖。

如需要，可將特殊功能存放器AUXR〔地址為8EH，將在后面介紹〕的第0位〔ALE制止位〕置1，來制止ALE操作，但執(zhí)行訪問外部程序存儲器或外部數(shù)據(jù)存儲器指令“MOVC〞或“MOVX〞時，ALE仍然有效。即ALE制止位不影響對外部存儲器的訪問。

：引腳第二功能，對片內(nèi)Flash編程，為編程脈沖輸入腳。PROG

圖2-2AT89S51雙列直插封裝方式的引腳PSEN4〕〔ProgramStrobeENable，29腳〕

片外程序存儲器讀選通信號，低電平有效。

并行I/O口引腳

1〕P0口：8位，漏極開路的雙向I/O口

當外擴存儲器及I/O接口芯片時，P0口作為低8位地址總線及數(shù)據(jù)總線的分時復用端口。

P0口也可用作通用的I/O口，需加上拉電阻，這時為準雙向口。作為通用I/O輸入，應(yīng)先向端口寫入1?？沈?qū)動8個LS型TTL負載。

2〕P1口：8位，準雙向I/O口，具有內(nèi)部上拉電阻。

準雙向I/O口，作為通用I/O輸入時，應(yīng)先向端口鎖存器寫1。

P1口可驅(qū)動4個LS型TTL負載。

P1.5/MOSI、P1.6/MISO和P1.7/SCK

可用于對片內(nèi)Flash存儲器串行編程和校驗，它們分別是串行數(shù)據(jù)輸入、輸出和移位脈沖引腳。

3〕P2口：8位，準雙向I/O口，具有內(nèi)部上拉電阻。

當AT89S51擴展外部存儲器及I/O口時，P2口作為高8位地址總線用，輸出高8位地址。

P2口也可作為普通的I/O口使用。當作為通用I/O輸入時，

應(yīng)先向端口輸出鎖存器寫1。P2口可驅(qū)動4個LS型TTL負載。

4〕P3口：8位，準雙向I/O口，具有內(nèi)部上拉電阻