交通控制器的設(shè)計(jì)與分析

第6章交通控制器的設(shè)計(jì)與分析6.1系統(tǒng)設(shè)計(jì)要求

6.2系統(tǒng)設(shè)計(jì)方案6.3主要VHDL源程序6.4系統(tǒng)仿真/硬件驗(yàn)證6.5設(shè)計(jì)技巧分析

6.6系統(tǒng)擴(kuò)展思路

6.1系統(tǒng)設(shè)計(jì)要求設(shè)計(jì)一個(gè)由一條主干道和一條支干道的集合點(diǎn)形成的十字交叉路口的交通燈控制器，具體要求如下：(1)主、支干道各設(shè)有一個(gè)綠、黃、紅指示燈，兩個(gè)顯示數(shù)碼管。(2)主干道處于常允許通行狀態(tài)，而支干道有車來(lái)才允許通行。(3)當(dāng)主、支道均有車時(shí)，兩者交替允許通行，主干道每次放行45s，支干道每次放行25s，在每次由亮綠燈變成亮紅燈的轉(zhuǎn)換過程中，要亮5s的黃燈作為過渡，并進(jìn)行減計(jì)時(shí)顯示。6.2系統(tǒng)設(shè)計(jì)方案交通控制器擬由單片的CPLD/FPGA來(lái)實(shí)現(xiàn)，經(jīng)分析設(shè)計(jì)要求，擬定整個(gè)系統(tǒng)由9個(gè)單元電路組成，如圖6.1所示。圖6.1交通控制器的內(nèi)部邏輯結(jié)構(gòu)原理圖6.3主要VHDL源程序6.3.1交通燈控制器JTDKZ的VHDL源程序--JTDKZ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYJTDKZISPORT(CLK，SM，SB:INSTD_LOGIC;MR，MY，MG，BR，BY，BG:OUTSTD_LOGIC);ENDENTITYJTDKZ;ARCHITECTUREARTOFJTDKZISTYPESTATE_TYPEIS(A，B，C，D);SIGNALSTATE:STATE_TYPE;BEGINCNT:PROCESS(CLK)ISVARIABLES:INTEGERRANGE0TO45;VARIABLECLR，EN:BIT;BEGINIF(CLK'EVENTANDCLK='1')THENIFCLR='0'THEnS:=0;ELSIFEN='0'THENS:=S;ELSES:=S+1;ENDIF;CASESTATEISWHENA=>MR<='0';MY<='0';MG<='1';BR<='1';BY<='0';BG<='0';IF(SBANDSM)='1'THENIFS=45THENSTATE<=B;CLR:='0';EN:='0';ELSESTATE<=A;CLR:='1';EN:='1';ENDIF;ELSIF(SBAND(NOTSM))='1'THENSTATE<=B;CLR:='0';EN:='0';ELSESTATE<=A;CLR:='1';EN:='1';ENDIF;WHENB=>MR<='0';MY<='1';MG<='0';BR<='1';BY<='0';BG<='0';IFS=5THENSTATE<=C;CLR:='0';EN:='0';ELSESTATE<=B;CLR:='1';EN:='1';ENDIF;WHENC=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='0';BG<='1';IF(SMANDSB)='1'THENIFS=25THENSTATE<=D;CLR:='0';EN:='0';ELSESTATE<=C;CLR:='1';EN:='1';ENDIF;ELSIFSB='0'THENSTATE<=D;CLR:='0';EN:='0';ELSESTATE<=C;CLR:='1';EN:='1';ENDIF;WHEND=>MR<='1';MY<='0';MG<='0';BR<='0';BY<='1';BG<='0';IFS=5THENSTATE<=A;CLR:='0';EN:='0';ELSESTATE<=D;CLR:='1';EN:='1';ENDIF;ENDCASE;ENDIF;ENDPROCESSCNT;ENDARCHITECTUREART;6.3.245s定時(shí)單元的VHDL源程序--CNT45S.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT45SISPORT(SB，CLK，EN45:INSTD_LOGIC;DOUT45M，DOUT45B:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT45S;ARCHITECTUREARTOFCNT45SISSIGNALCNT6B:STD_LOGIC_VECTOR(5DOWNTO0);BEGINPROCESS(SB，CLK，EN45)ISBEGINIFSB='0'THENCNT6B<=CNT6B-CNT6B-1;ELSIF(CLK'EVENTANDCLK='1')THENIFEN45='1'THENCNT6B<=CNT6B+1;ELSIFEN45='0'THENCNT6B<=CNT6B-CNT6B-1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT6B)ISBEGINCASECNT6BISWHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="01101001";WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";WHENOTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";ENDCASE;ENDPROCESS;ENDARCHITECTUREART;6.3.35s定時(shí)單元的VHDL源程序--CNT05S.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT05SISPORT(CLK，EN05M，EN05B:INSTD_LOGIC;DOUT5:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT05S;ARCHITECTUREARTOFCNT05SISSIGNALCNT3B:STD_LOGIC_VECTOR(2DOWNTO0);BEGINPROCESS(CLK，EN05M，EN05B)ISBEGINIF(CLK'EVENTANDCLK='1')THENIFEN05M='1'OREN05B='1'THENCNT3B<=CNT3B+1;ELSECNT3B<="000";ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT3B)ISBEGINCASECNT3BISWHEN"000"=>DOUT5<="00000101";WHEN"001"=>DOUT5<="00000100";WHEN"010"=>DOUT5<="00000011";WHEN"011"=>DOUT5<="00000010";WHEN"100"=>DOUT5<="00000001";WHENOTHERS=>--DOUT5<="00000000";ENDCASE;ENDPROCESS;ENDARCHITECTUREART;6.3.425s定時(shí)單元的VHDL源程序--CNT25S.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT25SISPORT(SB，SM，CLK，EN25:INSTD_LOGIC;DOUT25M，DOUT25B:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYCNT25S;ARCHITECTUREARTOFCNT25SISSIGNALCNT5B:STD_LOGIC_VECTOR(4DOWNTO0);BEGINPROCESS(SB，SM，CLK，EN25)ISBEGINIFSB='0'ORSM='0'THENCNT5B<=CNT5B-CNT5B-1;ELSIF(CLK'EVENTANDCLK='1')THENIFEN25='1'THENCNT5B<=CNT5B+1;ELSIFEN25='0'THENCNT5B<=CNT5B-CNT5B-1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CNT5B)ISBEGINCASECNT5BISWHEN"00000"=>DOUT25B<="00100101";DOUT25M<="00110000";WHEN"00001"=>DOUT25B<="00100100";DOUT25M<="00101001";WHEN"00010"=>DOUT25B<="00100011";DOUT25M<="00101000";WHEN"00011"=>DOUT25B<="00100010";DOUT25M<="00100111";WHEN"00100"=>DOUT25B<="00100001";DOUT25M<="00100110";WHEN"00101"=>DOUT25B<="00100000";DOUT25M<="00100101";WHEN"00110"=>DOUT25B<="00011001";DOUT25M<="00100100";WHEN"00111"=>DOUT25B<="00011000";DOUT25M<="00100011";WHEN"01000"=>DOUT25B<="00010111";DOUT25M<="00100010";WHEN"01001"=>DOUT25B<="00010110";DOUT25M<="00100001";WHEN"01010"=>DOUT25B<="00010101";DOUT25M<="00100000";WHEN"01011"=>DOUT25B<="00010100";DOUT25M<="00011001";WHEN"01100"=>DOUT25B<="00010011";DOUT25M<="00011000";WHEN"01101"=>DOUT25B<="00010010";DOUT25M<="00010111";WHEN"01110"=>DOUT25B<="00010001";DOUT25M<="00010110";WHEN"01111"=>DOUT25B<="00010000";DOUT25M<="00010101";WHEN"10000"=>DOUT25B<="00001001";DOUT25M<="00010100";WHEN"10001"=>DOUT25B<="00001000";DOUT25M<="00010011";WHEN"10010"=>DOUT25B<="00000111";DOUT25M<="00010010";WHEN"10011"=>DOUT25B<="00000110";DOUT25M<="00010001";WHEN"10100"=>DOUT25B<="00000101";DOUT25M<="00010000";WHEN"10101"=>DOUT25B<="00000100";DOUT25M<="00001001";WHEN"10110"=>DOUT25B<="00000011";DOUT25M<="00001000";WHEN"10111"=>DOUT25B<="00000010";DOUT25M<="00000111";WHEN"11000"=>DOUT25B<="00000001";DOUT25M<="00000110";WHENOTHERS=>DOUT25B<="00000000";DOUT25M<="00000000";ENDCASE;ENDPROCESS;ENDARCHITECTUREART;6.3.5顯示控制單元的VHDL源程序--XSKZ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYXSKZISPORT(EN45，EN25，EN05M，EN05B:INSTD_LOGIC;AIN45M，AIN45B:INSTD_LOGIC_VECTOR(7DOWNTO0);AIN25M，AIN25B，AIN05:INSTD_LOGIC_VECTOR(7DOWNTO0);DOUTM，DOUTB:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYXSKZ;ARCHITECTUREARTOFXSKZISBEGINPROCESS(EN45，EN25，EN05M，EN05B)ISBEGINIFEN45='1'THENDOUTM<=AIN45M(7DOWNTO0);DOUTB<=AIN45B(7DOWNTO0);ELSIFEN05M='1'THENDOUTM<=AIN05(7DOWNTO0);DOUTB<=AIN05(7DOWNTO0);ELSIFEN25='1'THENDOUTM<=AIN25M(7DOWNTO0);DOUTB<=AIN25B(7DOWNTO0);ELSIFEN05B='1'THENDOUTM<=AIN05(7DOWNTO0);DOUTB<=AIN05(7DOWNTO0);ENDIF;ENDPROCESS;ENDARCHITECTUREART;6.3.6顯示譯碼器的VHDL源程序--YMQ.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYYMQISPORT(AIN4:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT7:OUTSTD_LOGIC_VECTOR(6DOWNTO0));ENDENTITYYMQ;ARCHITECTUREARTOFYMQISBEGINPROCESS(AIN4)ISBEGINCASEAIN4ISWHEN"0000"=>DOUT7<="